I want to drive a LVPECL_25 input on a bank with VCCO=2.5V with a 3.3V LVPECL signal. Xilinx has a nice app note on doing this with a Virtex ii and a Spartan 3, but I can't find anything concrete about doing it on a Virtex-4. Would you agree that it's safe to implement the same solution on a Virtex-4?
Here's the app note:
It's just a voltage divider. Are there any adverse effects to this?
Thanks, Dale