interfacing to multiple converters

Jun 25, 2005 4 Replies
M

Hi,



I need to interface 2 ADCs and 1 DAC to a Spartan-II FPGA running at



57.6MHz. My data (12-bits wide) needs to be sampled at 200kHz and to save pins I'm going to be using serial ADCs/DACs.

As I understand it, using the SPI protocol I would need to read/write



16-bit words at 200kHz needing 3.2Msps converters. From what I've read about SPI, all slave devices connected to the same master have to share the same I/O bus and have separate CS pins.


- What I can't understand is, if I need my 2 ADCs and 1 DAC to communicate with the FPGA simultaneously, how do I achieve this when they have to share the same bus?


- Are there application notes I could refer to for guidance (I haven't been able to locate any by googling)?


- Would I need separate serial clocks (SCLK) for each converter and can I generate the SCLK using counters, so for instance to get a 3.2MHz SCLK period, count 18 clock cyles in the 57.6MHz domain of the FPGA system clock?


-Do I have to feed SCLK into a clock output pin or a will a general I/O pin do?



thanks, Mees



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B

What is preventing you from having multiple SPI cores?

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H

I don't follow what you are trying to say.

"3.2Msps" looks like 3.2 mega samples per second yet your previous paragraph says "sampled at 200kHz".

SPI is a bit serial protocol. You will have to clock it fast enough to get all your data bits in one sample time. The converters don't sample any faster than your target sample rate - just the clock for the serial data path.

If you are using sigma-delta type converters, they may also use the serial clock to run some digital logic.

I suggest reading the data sheet for the converters you are considering. They should have timing diagrams.

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M

Hello,

thanks for your responses.

I am sorry.I guess I hadn't understood that you could have multiple SPI interfaces. The wording of what I've read and the diagrams indicate separate CS lines for each slave but appeared to imply that all the slaves were sharing the same MOSI, and MISO buses. My mistake.

I also see where I've gone wrong with the converter specification. I was confusing the converter throughput with the desired SCLK speed. The converters only need to have a bit sample rate of 200kHz, and then SCLK needs to be 3.2MHz in order to shift/sample the bits through.

Thanks again, Mees

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V

Hello,

I am not quite following, I think that there are two separate issues addressed.

One, If you have several devices sharing the same data bus but have different CS signals, where exactly is the problem? You need something like 12 samples * 200 Ksps * 3 devices = 7.2 MHz clock, which can run in robin-round fashion and access each 12 clocks a different SPI port be toggling corresponding CS. What the timing diagrams have to say about it???

Two, You do not need to generate SPI clocks if you are not required to by SPI devices, you already have 57.6 MHz clock, and just divide it by 8 and either use it as a clock if you have clock buffer (line) available, or as a "clock enable" for the existing. In the last option, a general I/O pin + FF would be just fine.

Vladislav

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