180 differential inputs each 800Mbps using V5

Test01 · 2007-05-31T01:39:04+00:00

We have an application where I need to feed 160 differential data inputs and 20differential clock inputs to the high end V5 FPGA. There is one differentialclock for every 8 differtnial data inputs. I would like to use LVPECL inputs forthis.160 differential data inputs will be running at 800Mbps20 Differenital clock inputs will be running at 400MHz. In order to provide DDRclock for 160 data channels.Inside the FPGA we would like to use 1:4 demux and convert the data bus to 640bits wide running at 200MHz so the FPGA fabric can handle it. Then the data willbe fed to either 640 bits wide internal FIFO (as deep as I can get) or if I hada choice then feed the 640 bits wide bus running at 200MHz to external highdensity FIFO. This may require need for another FPGA.I have seen Xilinx application note for supporting such configuration. But inour application we need a lot more data inputs.I would like to get your input on this. Is this possible using high end V5 FPGA?Thanks.

May 31, 2007 22 Replies

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Test01 19 years ago

Brian,

Thanks for sharing this information. Certiainly when doing the PCB layout, we will need to take the internal trace length of high speed (800Mbps) signals.

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Brian Davis 19 years ago

For V2: Download the HSPICE models, unzip, then look in the v2_pkg_flight subdirectory, which has excel files for each package.

Brian

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Brian Davis 19 years ago

The trace lengths, when available, can also be dumped using partgen to create an ASCII .pkg file

I believe PACE and Jim Wu's ADEPT will also display this information.

Brian

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