Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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data capture
Any (specific) advice on a simlpe and cheap Xilinx board for data capture? I want to capture about 5-10 minutes of digital data from an RF. The highest rate that I need to handle is 4-bit data at...
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16 years ago
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Ballistic chronograph using a Spartan 3E starter board
Hi, I'm trying to create a "chrono" to measure the muzzle velocity of a paintball gun. Basically, I'm just making a two gate system out of some IR leds and photosensors which will hook into my Spartan...
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16 years ago
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Matlab code in nios processor
hi. i have made a fuzzy system in matlab. i have converted that into a c code using the real time tool box of matlab. i want to import this code and run a NIOS processor, can i do it. i tried to...
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16 years ago
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Problem with UART EDK 9.2.02i
Helo! I'm using a newest ver. of ISE and EDK (with all SP) on Linux Ubuntu (last relese), and I expirience a problem with UART. I've created two identical basic projects, one using 9.1 (on Windows)...
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16 years ago
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FPGA decoupling calculation
Hi, i am currently trying to figure out the number and values of a decoupling network for a spartan3e 500k (powered by the triple power supply from texas instruments TPS75003) .. i dont have the...
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16 years ago
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Altera FPGA
Below Factory Direct!!! I have stock in Irvine California of 1,000 pieces of an EP2S60F672C5N . I will let them go far below factory direct pricing. Please advise. I also have 106 pieces of a...
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16 years ago
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bi-phase decoding
Can anyone point me to some VHDL code for decoding bi-phase mark and space formats. Thanks in advance...
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16 years ago
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How FPGA downconvert Giga SPS ADC data?
Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don't understand how to downconvert Giga Hz adc in FPGA. The new ADC, for example...
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16 years ago
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Sparkfun Spartean3e Board
Hi I have a SparkFun Spartan3e development board which uses an ATMEL AT45DB161D serial SPI flash for configuration. Here is a photo: I can program the FPGA using JTAG but can not figure out how to get...
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16 years ago
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VHDL Micron memorymodel.
I have the Spartan 3e starter kit. it has this model RAM on it (MT46V32M16). I have generated the memory controller for it, but I would like to play with it on ModelSim first to help me understand DDR...
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16 years ago
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New user of ModelSim XE III v6.2 Starter - problems simulating a simple RAM.
Hi I am very new to VHDL and in partuclar ModelSim, so of course I have a simple starting exercise to learn from. I want to simulate this RAM model: (thankyou John Aynsley from Doulos) using the...
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16 years ago
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Source of accurate frequency
This is slightly off-topic: I have mentioned before that I am in the process of designing (and manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 GHz in 1 Hz increments). We debated...
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16 years ago
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Fuzzy Fixed Point Calculating
Hello! Prompt please how it is possible to create fuzzy system Sugeno (ANFIS) with use fixed point calculations? Realisation on FPGA is planned further. Probably there is a literature where about it...
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16 years ago
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[paper]?FIR on GPU,CPU, FPGA, ASIC
Hi, I am looking for a paper that compare the achieved performance from implementing general a N taps FIR filter on CPU, GPU, FPGA and ASIC i googled not much in return thanks
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16 years ago
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Chipscope Inserter to Chipscope Analyzer
Hi, does anyone know if it is possible to create a Chipscope Analyzer Project including alle Trigger and Data Port names from a cdc-file? Greetz Helmut
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16 years ago
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