Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Matlab code in nios processor

hi. i have made a fuzzy system in matlab. i have converted that into a c code using the real time tool box of matlab. i...
0 comments posted 18yrs
posted by srimankk
0 comments posted 18yrs posted by srimankk

Problem with UART EDK 9.2.02i

Helo! I'm using a newest ver. of ISE and EDK (with all SP) on Linux Ubuntu (last relese), and I expirience a problem wi...
4 comments posted 18yrs
posted by piotr.nowak21
4 comments posted 18yrs posted by piotr.nowak21

FPGA decoupling calculation

Hi, i am currently trying to figure out the number and values of a decoupling network for a spartan3e 500k (powered by...
33 comments posted 18yrs
posted by kislo02
33 comments posted 18yrs posted by kislo02

Altera FPGA

Below Factory Direct!!! I have stock in Irvine California of 1,000 pieces of an EP2S60F672C5N . I will let them go far...
1 comments posted 18yrs
posted by jon
1 comments posted 18yrs posted by jon

bi-phase decoding

Can anyone point me to some VHDL code for decoding bi-phase mark and space formats. Thanks in advance...
5 comments posted 18yrs
posted by romans5_8
5 comments posted 18yrs posted by romans5_8

How FPGA downconvert Giga SPS ADC data?

Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don...
6 comments posted 18yrs
posted by rxjwg98
6 comments posted 18yrs posted by rxjwg98

Sparkfun Spartean3e Board

Hi I have a SparkFun Spartan3e development board which uses an ATMEL AT45DB161D serial SPI flash for configuration. Her...
3 comments posted 18yrs
posted by usenet
3 comments posted 18yrs posted by usenet

VHDL Micron memorymodel.

I have the Spartan 3e starter kit. it has this model RAM on it (MT46V32M16). I have generated the memory controller for...
8 comments posted 18yrs
posted by davidsullivan1974
8 comments posted 18yrs posted by davidsullivan1974

Source of accurate frequency

This is slightly off-topic: I have mentioned before that I am in the process of designing (and manufacturing in limited...
38 comments posted 18yrs
posted by peter
38 comments posted 18yrs posted by peter

Fuzzy Fixed Point Calculating

Hello! Prompt please how it is possible to create fuzzy system Sugeno (ANFIS) with use fixed point calculations? Realis...
6 comments posted 18yrs
posted by tsepkovsky
6 comments posted 18yrs posted by tsepkovsky

[paper]?FIR on GPU,CPU, FPGA, ASIC

Hi, I am looking for a paper that compare the achieved performance from implementing general a N taps FIR filter on CPU,...
1 comments posted 18yrs
posted by karl.polytech
1 comments posted 18yrs posted by karl.polytech

Chipscope Inserter to Chipscope Analyzer

Hi, does anyone know if it is possible to create a Chipscope Analyzer Project including alle Trigger and Data Port names...
2 comments posted 18yrs
posted by helmut.leonhardt
2 comments posted 18yrs posted by helmut.leonhardt

How is FIFO implemented in FPGA and ASIC?

Hi, Could anyone explain why FIFO is difficult to implement in FPGA and ASIC? and how is FIFO implemented in FPGA and AS...
16 comments posted 18yrs
posted by camwwang
16 comments posted 18yrs posted by camwwang

Xpower decoupling network summary

Hi, in the help file of Xpower it says that the standard report contains: A standard report contains: Power Summary The...
1 comments posted 18yrs
posted by kislo02
1 comments posted 18yrs posted by kislo02