Hi
I am very new to VHDL and in partuclar ModelSim, so of course I have a simple starting exercise to learn from. I want to simulate this RAM model: (thankyou John Aynsley from Doulos) using the testbench that I have pasted under this model. Everything works fine until I assert the OE signal, i.e. OE Byte'(others=>'U')); begin Data 'Z'); if CS = '0' then if OE = '0' then -- Read operation Data