Field-Programmable Gate Arrays

regarding DMA memory to memory copy in NIOS II

here is my codes. I want to verify the result and display at the end, however I got like "cdcd", what's wrong? thanks /...

4 comments posted 18yrs

posted by BigJamesLau

4 comments posted 18yrs posted by BigJamesLau

Power Supply Bypassing Presentation

Hi - Power supply bypassing being a hot topic in these parts, some folks may be interested in the following. According...

0 comments posted 18yrs

posted by bobsrefusebin

0 comments posted 18yrs posted by bobsrefusebin

My first Flash FPGA

Hi all, I started a book witht that titled in 2006, but never finished, as I found the sources now, well it is still un...

9 comments posted 18yrs

posted by Antti.Lukats

9 comments posted 18yrs posted by Antti.Lukats

equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90

i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90...

3 comments posted 18yrs

posted by chaitanyakurmala

3 comments posted 18yrs posted by chaitanyakurmala

Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)

When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's...

16 comments posted 18yrs

posted by noone

16 comments posted 18yrs posted by noone

Virtex4: LVDS-Inputs in banks with VCCO!=2.5V (again)

Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with...

2 comments posted 18yrs

posted by news_jan08

2 comments posted 18yrs posted by news_jan08

FA: Brand New Altera MasterBlaster up on Ebay

No reserve.

0 comments posted 18yrs

posted by jflan

0 comments posted 18yrs posted by jflan

Synplicy and Xilinx - no PAR

I've got major issues here. I've installed Xilinx 9.2i with the latest updates and service packs, and am trying to get...

3 comments posted 18yrs

posted by fg

3 comments posted 18yrs posted by fg

Xilinx Spartan 3A/DSP with Coregen 9.2i?

I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP...

0 comments posted 18yrs

posted by noone

0 comments posted 18yrs posted by noone

buying fpga kits in denmark

Hi , Can anybody give me some information on buying fpga kits in denmark? ..iam interested in the altera cyclone 3 star...

3 comments posted 18yrs

posted by deepakvr

3 comments posted 18yrs posted by deepakvr

Thoughts about memory controller problems

Hi, I tried to boot Linux on my FPGA-prototyped SoC system. The Linux image is running from SDRAM which is controlled b...

2 comments posted 18yrs

posted by jack.harvard

2 comments posted 18yrs posted by jack.harvard

Endpoint Block Plus v1.5 example design

Hello, I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core wit...

1 comments posted 18yrs

posted by miriemer

1 comments posted 18yrs posted by miriemer

OV7660 CMOS camera

Hi all, Am working with this camera. wanted to know if anyone else has worked with it before. I have a set of register...

0 comments posted 18yrs

posted by narashimanc

0 comments posted 18yrs posted by narashimanc

Fixedpoint Multiply/Accumulate in DSP48

Hi, am a little confused as far as the capabilities of the DSP48 go. I would like to implement a 18x35 MACC in (hopeful...

4 comments posted 18yrs

posted by ksulimma

4 comments posted 18yrs posted by ksulimma

Initialize RAM in IGLOO

Hi all. I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the...

3 comments posted 18yrs

posted by rgrworking

3 comments posted 18yrs posted by rgrworking