Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Trouble programming V4FX40
A working board has been respun to use a FX40 in place of a FX20. For some reason I can't program FPGA on the new board through Impact. I tried both 8.2 and 10.1. It says that Done didn't go high and...
22
|
15 years ago
|
22 | |
|
|
Altera Quartus Web Edition 8.0 available
I've just had an email from Altera about the availability of Quartus Web Edition 8.0. I'm in the process of downloading it. Hopefully It'll have finished before the system gets overloaded. Leon
6
|
15 years ago
|
6 | |
|
|
Cheating the FPGA clock speed
Hey all -- So I've got a design, the very vaguest outlines of which are beginning to gel. But one of the things that's becoming apparent is that it would benefit from real clock rates somewhere...
9
|
15 years ago
|
9 | |
|
|
Whitepapers are taking over the lost TechXclusives
Thanks for the whitepaper, Peter! WP335 - Creative Uses of Block RAM It's good to see the start of the conversion. I remember the BlockRAM tricks from one of the many helpful TechXclusives and am...
4
|
15 years ago
|
4 | |
|
|
Strange Virtex-4FX 8b10b encoding behaviour
Hi, im an sending with an Virtex4-FX 8b10b encoded data at 1.25Gbps. It is working fine in simulation, but the implementation sends incorrect data. (checked with a scope at the MGT output) Apparently...
—
|
15 years ago
|
— | |
|
|
Digital VSB (Vestigial Side Band) Modulator for Analog TV
The task of my student research project is to implement a digital VSB modulator for analog TV in an FPGA. The design has three inputs: CVBS (Color Video Baseband Signal) and audio1 (mono/left) as well...
3
|
15 years ago
|
3 | |
|
|
bape ked robot red monkey adidas jacket
=96 crown dsquared jacket prices, reviews, and ratings in Clothing and Accessories . Compare products and find the lowest prices on crown dsquared jacket china supplier at
—
|
15 years ago
|
— | |
|
|
Error while compiling uClinux image for Microblaze
Hi, I was trying to compile uClinux image for microblaze. For doing so I followed the step by step process given in But, while doing 'make all' I get the following error - " make[3]: Entering...
—
|
15 years ago
|
— | |
|
|
where is the IP address assigned to the fpga in Trimode Ethernet MAC Core???
I have to use the Trimode Ethernet MAC core for my FPGA project, which will send and recieve data while connected to LAN though an Ethernet cable. For that obviously some IP address should be assigned...
6
|
15 years ago
|
6 | |
|
|
FSM running with unstable clock
Hi, I have described a state machine running with an external pixel clock. As I could see on the oscilloscope the ScanDetect signal becomes high indicating that the pixel clock is stable. BUT the...
4
|
15 years ago
|
4 | |
|
|
fpga reprogrammable?
hi.... how many times cain i download .bit files onto an fpga? i use virtex2pro.... thanks vikram
8
|
15 years ago
|
8 | |
|
|
aurora channel initialization fails
hi, I am trying to run the aurora example given by xilinx on fpga board which have xc2vp50 I am using refclock which is connected to 125MHz single clock. I am not able to initialize the channel....
—
|
15 years ago
|
— | |
|
|
how to track down an optimised away signal
Using verilog and ISE 10.1. I add a reg to modify the design's behaviour. It works and it works correctly. The change is intended to invert the carry logic for some op-codes. However synthesis , using...
7
|
15 years ago
|
7 | |
|
|
how to prevent timer code firmware running on Microblaze from being optimised
Hi, I am trying to do the following on Microblaze. Here is the program structure. void main() { Xuint32 countvalue; enable_timer(); // do some stuff on Microblaze ... //some lines of code .......
10
|
15 years ago
|
10 | |
|
|
readmem[b|h]
"readmemh" or "readmemb" in Verilog for initializing memories should only work in simulations and not for ASICs, but I've seen posts saying that XST can recognize readmemh and readmemb for FPGAs, just...
2
|
15 years ago
|
2 |