FSM running with unstable clock

Hi,

I have described a state machine running with an external pixel clock. As I could see on the oscilloscope the ScanDetect signal becomes high indicating that the pixel clock is stable. BUT the clock is not stable for some while after Scdt becomes high. The clock seems to tune after some us. (stable clock should have around 100MHz) The clock is changing its frequency, high and low phases are symmetrical.

If the FSM is running with that clock and if Scdt='1' is used to start the FSM, can I trust the state changes of the FSM ?

Thank you for your opinion.

Rgds Andre

Reply to
ALuPin
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I would have thought that if the pixel clock frequency is lower tha standard before it locks, then you should be OK. Otherwise need to appl the maximum clock frequency as constraint to P&R tool.

Reply to
RCIngham

If the unstable clock runs directly into the chip (without using the DCM) your only concern is the shortest possible time between two rising (or falling) clock edges, which your design must accommodate. Frequency modulation is otherwise irrelevant. If you use a DCM, you must follow the rules for input cycle changes, as specified in the data sheet. Peter Alfke

Reply to
Peter Alfke

Thank you for your answers.

Rgds Andre

Reply to
ALuPin

You should be sure that if the FSM gets into an undefined state that it will be able to get out of that state in a reasonable number of clock cycles. Usually that is enough.

-- glen

Reply to
glen herrmannsfeldt

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