FSM running with unstable clock

I would have thought that if the pixel clock frequency is lower tha standard before it locks, then you should be OK. Otherwise need to appl the maximum clock frequency as constraint to P&R tool.

If the unstable clock runs directly into the chip (without using the DCM) your only concern is the shortest possible time between two rising (or falling) clock edges, which your design must accommodate. Frequency modulation is otherwise irrelevant. If you use a DCM, you must follow the rules for input cycle changes, as specified in the data sheet. Peter Alfke

Thank you for your answers.

Rgds Andre

You should be sure that if the FSM gets into an undefined state that it will be able to get out of that state in a reasonable number of clock cycles. Usually that is enough.

-- glen