Hi,
I have described a state machine running with an external pixel clock. As I could see on the oscilloscope the ScanDetect signal becomes high indicating that the pixel clock is stable. BUT the clock is not stable for some while after Scdt becomes high. The clock seems to tune after some us. (stable clock should have around 100MHz) The clock is changing its frequency, high and low phases are symmetrical.
If the FSM is running with that clock and if Scdt='1' is used to start the FSM, can I trust the state changes of the FSM ?
Thank you for your opinion.
Rgds Andre