Hey all --
So I've got a design, the very vaguest outlines of which are beginning to gel. But one of the things that's becoming apparent is that it would benefit from real clock rates somewhere between the obscene and the unthinkable.
Throwing lots of money at the problem seems to get me to 500 MHz, yet more can get me up to 550 MHz, but I could get a lot of other things to run much more smoothly if I could get clock rates out into the 650 MHz ballpark. That's for BRAMS and multipliers/DSP slices, not just the flops.
So I get to thinking about how the clock rate specs get figured out, and how they have to accomodate the slow silicon at the maximum operating temperatures. And that thought leads around in circles for a while, and ultimately leads to the following appalling question:
Anyone know anything about using Peltier modules, refrigerant pumping systems, or the like, to cheat up the speed of an FPGA? Is it even feasible to try to get a 20-30% overclock just from the joys of lower temperatures? Or do I just suck it up and deal with the rated clock speeds?