To all,
I have a counter that uses a control input that toggles which signal I am incrementing. Both count values are restricted to a range and so they always stay in this range and wrap around when they go to the end of the range. I have some status flags called "full_status" and "empty_status" to which when the two addresses are equal - a situation when one of the pointers catches up to the other - the flags are asserted. This assertion is to stay active until the control signal "get_store_ctl" toggles to allow the other pointer to increment. Unfortunately the status flags given one state of the "get_store_ctl" is supposed to stay asserted when "get_addr = store_addr" until as I mentioned the "get_store_ctl" changes and the pointers themselves are not supposed to increment at all as I try to freeze this. This is not what happens, as the pointer itself keeps incrementing.
The section that is not functioning according to my description is the section in the VHDL code that has the IF statement that compares "updated_addr = comp_addr". Can someone correct the piece of VHDL code below? Again I'm expecting that once the flags are asserted according then the output address is always supposed to stay constant and not increment. This is what I would like to happen but for some reason it's not working this way.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL;
ENTITY free_memory_addr_counter IS GENERIC (NUM_OF_BITS : POSITIVE :=32); PORT( CLK :IN STD_LOGIC; RST_N :IN STD_LOGIC; PTR_EN :IN STD_LOGIC; GET_STORE_CTL :IN STD_LOGIC; EMPTY_FLAG :OUT STD_LOGIC; FULL_FLAG :OUT STD_LOGIC; GET_ADDR_PTR :OUT STD_LOGIC_VECTOR (NUM_OF_BITS-1 DOWNTO 0); STORE_ADDR_PTR :OUT STD_LOGIC_VECTOR (NUM_OF_BITS-1 DOWNTO
0); OUT_ADDR :OUT STD_LOGIC_VECTOR (NUM_OF_BITS-1 DOWNTO 0) ); END ENTITY free_memory_addr_counter;ARCHITECTURE main_cntr_rtl OF free_memory_addr_counter IS
-- Define parameters signal full_status :std_logic; signal empty_status :std_logic; signal get_addr :std_logic_vector(NUM_OF_BITS-1 DOWNTO 0); signal store_addr :std_logic_vector (NUM_OF_BITS-1 DOWNTO 0); signal updated_addr :std_logic_vector (NUM_OF_BITS-1 DOWNTO 0); signal comp_addr :std_logic_vector (NUM_OF_BITS-1 DOWNTO 0);
constant START_MEM_ADDR :std_logic_vector(NUM_OF_BITS-1 DOWNTO 0) := x"01000000"; constant END_MEM_ADDR :std_logic_vector(NUM_OF_BITS-1 DOWNTO 0) := x"01000003"; --:= x"0100FFFF";
BEGIN
PROCESS (CLK, RST_N) BEGIN IF (RST_N = '0') THEN get_addr