cmos delay vs temperature

I found one old Fairchild appnote that has some numbers

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which averages to around +3000 ppm/degC, or about +3 ps per ns of prop delay per degree C. That's with 50 pF loading, sorta high.

This is HC, pretty old technology.

I have a vague impression that the innards of a typical FPGA may be better. Here's a ring oscillator inside an Altera FPGA, which looks close to +1000 PPM/degC delay tempco. But that's deep inside, probably CLB and not interconnect limited, and i/o cells may be different.

ECL is much better, generally way under 1000 PPM.

Do any semiconductor jocks have any comments on cmos tempco?

Do any of the FPGA design tools report timing tempcos? I don't drive those tools myself.

I suppose one could tweak Vcc vs temp to null out a native tempco.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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John Larkin
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Den torsdag den 16. februar 2017 kl. 21.19.20 UTC+1 skrev John Larkin:

The old Xilinx tools had the option the option to run timing analysis at different temperatures, the new tool doesn't Xilinx claims it no longer makes sense because for complex devices like FPGAs it is no longer as a simple as colder=faster, hotter=slower

Reply to
Lasse Langwadt Christensen

Better still, use a PLL to lock the ring oscillator to a reference by servoing Vcore. ;)

Cheers

Phil Hobbs

Reply to
pcdhobbs

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;)

Reply to
Lasse Langwadt Christensen

That is done in FPGA-based time-to-digital converters, where one derives a time stamp by latching the pattern in an unclocked shift register or ring oscillator. The shift register prop delay is continously tuned.

Lots of papers online.

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John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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Reply to
John Larkin

the Xilinx idelay/odelay does sort of the reverse, it takes a 200MHz reference clock and uses that to control the taps to get constant delays on output and inputs

-Lasse

Reply to
Lasse Langwadt Christensen

I've seen timing analysis tools that will evaluate the design at high temp, low temp or typical, but I've never seen them offer tempcos. If you analyze your design at high and low temps it would be easy enough to calculate of course. Analyze it at typ temp just to make sure it's linear. But this may not be what you want. These are not real numbers. They are worst case production run numbers. I have no idea how they will compare to real world numbers.

I know the timing analysis tools are not always accurate. 15 years ago Altera had moved on to Quartus for new work and MAX+II was only used for existing designs on previous generation chips. Their delay calculations for heavily loaded routes was not accurate and our designs would fail when the part warmed up. Quartus didn't support the chips then, so we had to shotgun it by routing some 10 to 20 runs a night and then testing them the next day with a chip heater.

The delay isn't all silicon, so I don't know how it would be calculated over temp. What happens to the R and the C of metal runs on a chip with temperature? Is that significant? The actual delay is. Or that may be the Si switches used to interconnect the routes. Don't know. That's kinda the point of digital techniques. Deal with the pesky analog effects to get them out of the picture so we can focus on the complicated stuff.

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Rick C
Reply to
rickman

Until some time ago, most FPGA timing analysis tools used the worst-case parameters from the datasheets, that should have been characterized pretty well. In fact, it was completely normal that a real design in a lab environment performed a lot better than the timing simulation would suggest.

However I'm not aware of the "last" (5-10 years) evolutions of the design tools.

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Fletto i muscoli e sono nel vuoto.
Reply to
dalai lamah

It's likely not the same for positive and negative edges (output delay due to Pmos having higher capacitance or ON resistance). It's also gonna be different for HCT parts, and for Schmitt-trigger parts.

Since switching occurs at potentials that are within the logic margin, you should expect significant unit-to-unit variation, too. It's surprising, really, that they bothered measuring (and only at 5V, on a family that runs from 2 to 6V).

Some XOR designs, using transmission gates, would be interesting to characterize. The 'hc139 outlier is probably due to the count of logic stages. It's a 3-in decoder, and the CD4514 (4-in decoder) has 8 gates between inputs and outputs according to the old RCA datasheet.

Reply to
whit3rd

I misread: the datasheet says the CD4515 has 8 gates of delay, the CD4514 has 7 gates.

Reply to
whit3rd

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