One now near-forgotten logic design paradigm is "delay-line logic", where tapped delay lines were used to sequence digital logic things. DEC did a lot of this in the PDP-8 days, and early DRAM controllers tended to work this way. I suppose passive LC delay lines were cheaper than flipflops and such, in those distant days.
But I just came across a design done in the early 1990's that was a mix of CPLDs and delay lines. I guess some old-timer did it. The worst example was one Atmel CPLD with ***five*** delay lines hooked to it. Several others have two or three.
The delay lines are "MSX1000SA050" on the schematic. One input, 5 outputs at 10 ns delay steps, +5 and ground, so it may be one of those TTL-buffered-LC things. I don't know if people were doing silicon delay lines ca 1990.
Does this part number sound familiar to anybody? I've googled and can't find the manufacturer.
John