cmos delay vs temperature

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I found one old Fairchild appnote that has some numbers

which averages to around +3000 ppm/degC, or about +3 ps per ns of prop
delay per degree C. That's with 50 pF loading, sorta high.

This is HC, pretty old technology.  

I have a vague impression that the innards of a typical FPGA may be
better. Here's a ring oscillator inside an Altera FPGA, which looks
close to +1000 PPM/degC delay tempco. But that's deep inside, probably
CLB and not interconnect limited, and i/o cells may be different.

ECL is much better, generally way under 1000 PPM.

Do any semiconductor jocks have any comments on cmos tempco?  

Do any of the FPGA design tools report timing tempcos? I don't drive
those tools myself.

I suppose one could tweak Vcc vs temp to null out a native tempco.


John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: cmos delay vs temperature
On 2/16/2017 3:19 PM, John Larkin wrote:
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I've seen timing analysis tools that will evaluate the design at high  
temp, low temp or typical, but I've never seen them offer tempcos.  If  
you analyze your design at high and low temps it would be easy enough to  
calculate of course.  Analyze it at typ temp just to make sure it's  
linear.  But this may not be what you want.  These are not real numbers.  
  They are worst case production run numbers.  I have no idea how they  
will compare to real world numbers.

I know the timing analysis tools are not always accurate.  15 years ago  
Altera had moved on to Quartus for new work and MAX+II was only used for  
existing designs on previous generation chips.  Their delay calculations  
for heavily loaded routes was not accurate and our designs would fail  
when the part warmed up.  Quartus didn't support the chips then, so we  
had to shotgun it by routing some 10 to 20 runs a night and then testing  
them the next day with a chip heater.

The delay isn't all silicon, so I don't know how it would be calculated  
over temp.  What happens to the R and the C of metal runs on a chip with  
temperature?  Is that significant?  The actual delay is.   Or that may  
be the Si switches used to interconnect the routes.   Don't know.  
That's kinda the point of digital techniques.  Deal with the pesky  
analog effects to get them out of the picture so we can focus on the  
complicated stuff.


Rick C

Re: cmos delay vs temperature

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Until some time ago, most FPGA timing analysis tools used the worst-case
parameters from the datasheets, that should have been characterized pretty
well. In fact, it was completely normal that a real design in a lab
environment performed a lot better than the timing simulation would

However I'm not aware of the "last" (5-10 years) evolutions of the design

Fletto i muscoli e sono nel vuoto.

Re: cmos delay vs temperature

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I am not an expert in this field either, but to my knowledge, things got mu
ch more complex with the smaller process geometries.

Generally things will still become faster at higher supply voltage and lowe
r temperature, but I had also designs which (according to the timing analyz


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