5 years ago
which averages to around +3000 ppm/degC, or about +3 ps per ns of prop
delay per degree C. That's with 50 pF loading, sorta high.
This is HC, pretty old technology.
I have a vague impression that the innards of a typical FPGA may be
better. Here's a ring oscillator inside an Altera FPGA, which looks
close to +1000 PPM/degC delay tempco. But that's deep inside, probably
CLB and not interconnect limited, and i/o cells may be different.
ECL is much better, generally way under 1000 PPM.
Do any semiconductor jocks have any comments on cmos tempco?
Do any of the FPGA design tools report timing tempcos? I don't drive
those tools myself.
I suppose one could tweak Vcc vs temp to null out a native tempco.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement