Why can't you read and understand my question? Your schematic looks like the source is connected to the gate. Is that what you intended??? I understand the parallel, but are all the gates supposed to be connected to all the sources too? Is this a language issue?
On a sunny day (Wed, 17 Sep 2014 03:57:05 -0400) it happened rickman wrote in :
Yes they are all connected
My understanding is that when you connect the gate to the source it just becomes a resistor. What is the FET doing in this circuit?
On a sunny day (Wed, 17 Sep 2014 04:57:44 -0400) it happened rickman wrote in :
Decoration
Ok, thanks for the clear explanation. :)
It's even not true modulo, just an overflow detector.
A decade ago I developed a sine/cosine calculator for an FPGA-based quadrature mixer. It was able to run at ~300MHz on the old Cyclone v. 1.0, far faster than needed -- the ADC was clocked at 65MHz, the DAC at ~100MHz. It used just one multiplier and a BRAM and produced results accurate to ~17.3 bits, again far better than needed.
Best regards, Piotr
On a sunny day (Tue, 16 Sep 2014 18:25:52 +0100) it happened "Kevin Aylward" wrote in :
1540 MHz 1 1.4 Vdc X 1605 MHz 3.6 3.9 Vdc X
A DDS that resets the counter at some target value is going to have interesting jitter glitches.
Am 16.09.2014 um 19:25 schrieb Kevin Aylward:
Actually, its in the range of 10 MHz to 50 MHz for the sweet area over all constraints of circuit design, xtal design, performance and size for actual xtal oscillators. That's why the main xtal oscillator venders have lots of product in that range.
There are a lot of trade offs like aging, power supply sensitivity, hysteresis, availability of asic processes with the right components, cost etc.
Exactly the point of why one must multiply up.
I did already make that point in this thread. Its a necessary evil.
There is not any realistic alternative, but to multiply up, if you actually need high frequency references.
Sure, multiplying up from 10 MHz to 10 Ghz is probably not really an option for low pn. 200Mhz is more realistic. Still tricky with the xtal oscilater at that frequency, -130 dBc is probably not out of the question though.
The point is that, if the discussed system would fail with the phase noise due to temperature variations of an LC tank filter extracting a clock, then the system would fail anyway, assuming no errors in my calculations.
I make it:
PN = Q . dKL/dT . KT/W
dKL/dT inductance change with temperature KT rms amplitude of temperature change, changing sinusoidal at radian frequency W.
Assuming 1 deg over 1 minute, gets around -95dBc/hz at 1Hz, even faster at 1 deg/sec around -60 dBc/hz phase noise at 1Hz
A typical 10Mhz xtal oscillator will hit maybe -70dBc at 1Hz. A 40Mhz 3rd overtone, divided down by 4 might hit -90dBc. The point being is that any phase error of a tank is going to be of the order of what you want get from a high quality xtal oscillator. So, if a tank wont work, neither will will a xtal oscillator. Without a xtal oscillator, you're knackered anyway.
For reference, the tank is not being used as the tuning device of an oscillator. If it were, any shift in L would lead directly to a frequency shift, which would result in much greater phase noise.
I don't understand what you are saying here. All oscillators will, essentially, have a low frequency noise at 30db/decade. This is because all devices, have 1/f noise. The LC gives the 20db/decade bit, until it flattens at very low frequency (Lorentz). There is a sort of exception in principal, but in realty achieving it is not going to happen in practice. e.g.
Regarding op amp. It is noted that large audio bipolar transistors are available with very low 1/f noise. Not so for available HF transistors.
Kevin Aylward
No, they are not connected to the gates.
when reading schematics, the cross over is not connected unless its shows a hard dot at the intersection. Some may elect to use the hump method.
Also, when lines dead end to other lines, they are connected.
In this case, they are just crossing over on paper.
Jamie
Please go back to your schematic and tell me the gate and source of the right hand FET are not connected based on the rules you just provided. It is the right hand FET that is repeated. I am assuming the left one is separate and the right one is part of the parallel group?
Assuming the the first FET gate is intended to be connected to the other gate and not to any of the sources, what is the current path for the high voltage side of the transformer, through the gate and the drain?
I don't know what you intended because it is clear to me there is an error in the schematic. I just don't know how many errors and where.
Opps, sorry I called it "your" schematic. I got you mixed up with Jan. So the questions should be for Jan, but I can't seem to get a civil answer out of him. I guess he has not yet figured out the schematic has errors. Silly boy.
Why do you think that? Resetting a synchronous counter puts the clock edges in the same place as any other transition.
And you would have presumably chosen a non-binary modulus in order to have an integral number of DAC updates in your repeat cycle, so the DAC outputs - the steps in your staircase approximation to your sinewave - will always be evenly spaced.
The modulus would be chosen to give a synthesized frequency that is exact rather than just very close. I assume when you say "DAC updates" you mean the sine table lookups. The DAC updates on every clock. If your frequency is right then yes, there will be an integral number of clocks in your cycle which may or may not be a sine wave period.
No, more like shaking a bitch off the leg.
Am 17.09.2014 um 19:39 schrieb Kevin Aylward:
That proves only that you have a crappy 10 MHz, and a 3/4-crappy 40 MHz one. The 10811A does -90dBc at 10 MHz/1Hz without dividing and has been in most HP signal generators and counters in the last 40 years. That _is_ fire&forget mass production, and optimized for long term stability and not for phase noise.
Or take the Morion MV89, currently available on ebay from old mobile base stations in China: -105 dBC @1Hz, 5 MHz. The 10 MHz units run internally on 5 MHz and double internally. Tells us something about sweet spots?
<Or the comments of Randall W. Rhea in "Oscillator Design and Computer Simulation" ISBN 0-07-052415-7, highly recommended:
"The highest unloaded Q in the HF region .. is achieved by using a lower frequency quartz crystal and operating it at the 3rd or 5th overtone. The resulting series resistance is greater but the motional inductance is increased significantly and more than compensates for the higher resistance. [....consequences for Driscoll oscs.....] A typical high precision 5 MHz 5th overtone crystal resonator in a vacuum-sealed glass holder might have a resistance of 120 Ohms and a motional inductance of 8 Henries. This is an unloaded Q of over 2 million."
Well, those crystals do not fit into HC52/U.
The point being is
There are people who can handle multipliers. For example: <
If your onchip inductors have lousy Q and capacitors take up too much area, that's not the fault of the oscillators/multipliers, and also not your fault, but you'll have to make the best out of it.
And the phase noise plots on page 8 of the LT datasheet are on 3 and
4 GHz, that's not advertizing creativity as it was suggested, they have done their homework.That was not in the context of oscillators but in that of my low noise preamp and the battery noise voltage measurements that I mentioned some
50 posts above. Somewhere else on the net, the designer of the AD797 was puzzled because of the 30 dB slope 1/f in the voltage noise of the batteries and proposed to investigate that further. A paper of the NIST timefreq group also showed flatter 1/f, partly none down to 10 Hz.But loud wideband noise from 100 MHz downconverted to DC was perfectly flat with my preamp & FFT analyzer downto 0.1 HZ, so the 1/f really seems to come from the batteries. Some doubts remain.
regards, Gerhard
On Thu, 18 Sep 2014 02:12:03 +0200, Gerhard Hoffmann Gave us:
Somewhere in northern Siberia?
most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.
dedicated
stuff
feared.
And you are not receiving what i am saying, there must be a good market for the dedicated chips or there wouldn't be so many of them. I never claimed that DDS could not be done in other devices.
?-)
Ok, then neither of us understands what the other is saying... :P
Sure, ADI sells enough of these things to make a profit. Still a lot of DDS are done other than in dedicated chips. You were waxing about the limitations of dedicated DDS chips. Fine, but that has no bearing on any of the other implementations.
Yet another ankle biter. OUCH! :(
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