PLL tricks

On a sunny day (Tue, 23 Sep 2014 05:40:18 -0700 (PDT)) it happened snipped-for-privacy@yahoo.com wrote in :

Well ,as I stated I'd like to know more about his 'reference' 10 MHz, the absolute time and phase is bogus. Low jitter can be done with a large time constant PLL loop filter. I think that whole laser setup is well eh, CRAP.

Do not see the problem, I am within 3 or ps (2 degrees) after several conversions down from 1.something GHz. People have proposed exact dividers already in this thread, bit of filtering.. But even with some jitter 80 kHz can be filtered out, a second more accurate phase comparator switched in, its all old hat.

ote:

tair-case approximation to the desired 10MHz waveform.

ew transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog o utput delay".

pm

Of course. John Larkin spelled this out - initially a little less than perf ectly clearly - when he started this thread, and he's clarified exactly wha t he wants to do in considerable detail since then.

n,

It's a delay you could calibrate. I was looking at the Analog Devices AD991

If one dug around a bit deeper, one might find a better specified part, but - as has been repeatedly mentioned here - you can always put the DDS logic into a programmable logic part and clock your own DAC with a suitably prec ise clock derived directly from the 155.52 MHz VCXO source.

Back when I was directly interested, all the best fast DAC's relied on ECL logic levels at all the digital inputs, because it provided a much cleaner analog environment for the analog side of the device.

So it may be an objection to a particular DDS chip, but it's not an objecti on to using DDS to generate 10MHz from the 155.52 MHz clock output.

And if you are using a product phase detector - either a multiplier or full

-wave switching phase detector - you can do almost as well with a fractiona l-n approximation to your 10MHz output - basically alternating dividing 155 .52MHz by 15 almost half the time - 59 out of 125 cycles - and by 16 the re st of the time 69 out of 125 cycles. The phase is out by up to 6.4nsec in 1

The DDS approach would generate a whole lot less phase noise in the first p lace, but it is more complicated - though a lot less messy than you seem to think.

John enthusiasm for using a non-linear bang-bang phase detector rather limi ts his option. I thinks it's actually a very bad approach for his particula r problem.

If you have a hub, you can power 100,000 mosquitoes. ;)

Cheers

Phil Hobbs

No problem. I'll be buying a VCXO with LVPECL outputs.

It's hard to get simpler than one d-flop.

My biggest concerns are filtering and squaring up to 10 MHz reference sine wave, and the loop dynamics/noise. A little mental math suggests that the 80 KHz bangbang loop will work, as long as the VCXO has good open-loop jitter in the, roughly, milliseconds time scale.

I don't have tools to simulate this. Spice doesn't look appropriate. If we get this job (chances are pretty good) the first thing to do is a PLL breadboard.

Correct. Even if you use a non-binary DDS to nail the frequency ratio, the added errors would be ghastly.

Am 23.09.2014 um 19:35 schrieb John Larkin:

...

Take a look at the LTC6957 family. Also, the differential limiter on Wenzels web site is said to be good; recently, there was some discussion on this on the timenuts list IIRC.

You already know the Oliver Collins paper on bandwidth limiting and slope amplification.

regards, Gerhard

If you used a product phase detector - like an AD834 - or even a switching full-wave phase detector like the Faulker and Harding long-tailed pair - it is dead easy. Not-invented-here concentration on the bang-bang sequential phase detector is not doing you any good at all.

Of course.

It's actually remarkably easy, but while you can lead a horse to water, you can't make him drink.

You don't have to. if you choose your phase detector sensibly.

A little more would suggest that a product-type phase detector would work b etter, but they are not-invented-here devices.

A new pair of eyes on the problem might help more.

es. An AD834 might be one example.

able

ow-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I s uspect that a two pole filter with a bit of ringing would distort the expon ential segments between steps into something close enough to a sine wave fo r most purposes.

sidual - systematic - spurs can average out over the 12.5usec repeat c...

Sure. But it eliminates a whole lot more that are intrinsic to your Bang-ba ng detect at 80KHz approach.

Not that you have clue what they might be. The ghastliness is all in workin g out what they actually are.

tair-case approximation to the desired 10MHz waveform.

ew transistors in that signal path. And you've got total control over rails feeding the DDS chip. The DDS doesn't have any kind of "wandering analog o utput delay".

pm

n,

And it's a very poor one.

In my previous response to this post I mentioned that you could roll your o wn DDS and get pick your own - calibrated - delay through the DDS, which go t me thinking about what a roll-your-own DDS might look like.

Doing the usual minimal search on just-fast-enough DACs threw up the Analog Devices

which are just fast enough - with a maximum up-date rate of 175MHz - and ha ve a typical output propagation delay of 4nsec.

is faster, and not all that expensive, and offers a typical output propagat ion delay of 1nsec. No doubt one could do better.

The rest of the DDS could be jammed into a single programmable logic device , and would consist of an 11-bit address counter that counted edges of the

One of the nice things about working at a fixed frequency is that you can u se the DAC to drive an integrator, generating a straight-line segment appro ximation to a sine wave, rather than the usual DDS stair-case. A single pol e of low-pass filtering on the DAC output current - about 3nsec worth - cou ld smooth the transitions between the straight-line segments and smear out any switching glitches.

Of course you'd have to add a slow DC-feedback loop around the integrator t o keep the output centered around 0V (or whatever fixed DC voltage took you r fancy) but that's not rocket science.

It's taken me a surprisingly long time to wake up to this point. You could also integrate the output of conventional DDS chip to get the same effect.

Perhaps you could explain to me why you need a fast DAC if you are going to filter it through a low pass filter?

When you say "integrator" do you mean integrator or low pass filter? I'm unclear on what waveform you would expect from an integrator. Are you going to set the values in your sine table to be the deltas rather than the sine values? That might make sense.

ote:

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stair-case approximation to the desired 10MHz waveform.

few transistors in that signal path. And you've got total control over rai ls feeding the DDS chip. The DDS doesn't have any kind of "wandering analog output delay".

ison, you've added an uncalibrated delay that cannot be removed, ditto any noise or jitter produced in the DDS, that's my point.

ur own DDS and get pick your own - calibrated - delay through the DDS, whic h got me thinking about what a roll-your-own DDS might look like.

alog Devices

d have a typical output propagation delay of 4nsec.

agation delay of 1nsec. No doubt one could do better.

vice, and would consist of an 11-bit address counter that counted edges of the 155.52MHZ clock, from 0 to 1943 and rolled over to 0 after 1943, to add ress a 1944-entry sine lookup table, whose output would drive the DAC (via a latch to re-sycnronise the digital output to the 155.52MHz clock).

an use the DAC to drive an integrator, generating a straight-line segment a pproximation to a sine wave, rather than the usual DDS stair-case. A single pole of low-pass filtering on the DAC output current - about 3nsec worth - could smooth the transitions between the straight-line segments and smear out any switching glitches.

or to keep the output centered around 0V (or whatever fixed DC voltage took your fancy) but that's not rocket science

uld also integrate the output of conventional DDS chip to get the same effe ct.

John Larkin wants to lock his 155.52MHz local clock to the 10MHz reference clock distributed around the laser farm, and he wants to do it with sub-pic osecond long term stability.

There's a delay between clocking the DDS digital data on an edge of the 155 .52MHz clock, and the analog output from the DAC going into the integrator.

There's a further delay through the integrator, but if you wrap it around a really fast op amp, it won't be big either.

The delays, and - more important - all the drifts on these delays - add up and eat into John's error budget. The crudest - but often the most effectiv e way of minimising - the drifts on the individual delays is simply to keep them small.

It might be an argument for going for fractional-n rather than DDS for gett ing the derived 10MHz waveform. With that you are definitely stuck with a l inear phase detector, but there are a up to 6.4nsec of phase excursion on e ach nominally 10MHz edge, but the delays can all be through ECLinPS logic.

I mean an integrator.

The integral and the derivation of a sine wave is a cosine wave. It's not r ocket science.

I didn't need a recap of the whole thing. The question is why would you worry about a couple of nanoseconds on the DAC when you are running the output through a filter which delays it further likely by a larger amount?

No, but you are messing further with the delays which you seem to say you care about. In reality the delays on this portion of the circuit are moot. They will be calibrated out.

But this does give me some interesting ideas on better ways to do the DAC.

That was less than obvious.

You won't use much filtering on the DAC output before you put it into the p hase detector of the PLL.

With a staircase approximation, I was thinking of a slightly ringing two-po le filter which might have had a delay of about 6nsec, and with the straigh t-line segment approximation you'd get coming out of an integrator, one pol e and about 3nsec would probably be plenty - and you could probably get awa y with with rather less.

After the phase detector has turned any phase error into a DC signal, you t hen low-pass filter like hell, but you can set up the PLL feedback path to cope with this and still offer a dead-beat response, albeit with a delay of a millisecond or so, if I've understood John Larkin's ambitions correctly.

ot rocket science.

The frequency response of the op amp around which the integrator is built w ill introduce a delay, but - with a fast op amp - not a big one

Do try to sell them to Analog Device, Linear Technology and the rest - they 've been looking for better ways to realise special purpose DACs for some t ime now.

The DAC and the following low-pass are there only to smooth out the

If you tweak the NCO to make the MSB a 50% duty cycle square wave on average, you can pipe it straight into a DB mixer with your sine-wave 10MHz reference at the other input to make the phase error signal.

Jeroen Belleman

I think the issue here is the phase-to-voltage linearity of the phase detector. Fractional-n puts up to 6.4nsec - typically about 3nsec - phase excursions on pretty much every clock edge, and you want them to cancel out - to sub-picoscend accuracy over the 12.5usec it takes the cycle to repeat.

DDS offers a much better approximation to a 10MHz sine wave going into the phase detector and puts a correspondingly lower demand on it's linearity.

John Larkin is infatuated with his - totally non-linear - edge driven bang-bang phase detector, so fractional-n doesn't get a look-in.

Tricky. The fractional-N approximation from a 155.52MHz clock to a

You can split the 16 cycle segments into 8+8 but the 15 cycle ones are 7+8.

The crudest way of getting there is a 250 entry look-up table - 194 divide by eight and 56 divide by seven. You end up with 30 three divides by eight followed by one divide by seven, plus 26 four divides by eight followed by one divide by seven.

Perhaps, but DDS is not always about PLL. There are plenty of times when you want a sine wave as your output.

I haven't worked out the details, but I might try to make an NCO with a phase accumulator constrained to values between -972 to 971 when interpreted as a signed 2's-complement number. Add 125 on each beat of the 155.52MHz clock and the sign bit ends up a fair approximation of a 50% duty cycle square at exactly 10MHz on average, with the phase error pattern repeating every 12.5us. That's an FPGA job, of course. Reclock the sign bit using an ECL FF clocked with the original clean

Removing the cycle-to-cycle phase variations is the loop filter's job. They average out over 12.5us.

Jeroen Belleman

Of course logic is cheap in an FPGA so such a counter is not a big deal to implement. But it can be smaller/faster to use a phase accumulator that ranges between 0 and 971 followed by a divide by two FF to make the square wave. Rather than use the MSB, make it a subtractor so that the carry out is your flag to both reload the accumulator with the adjusted value for the modulus and to toggle the square wave FF.

If you need something like this to run as fast as possible, the carry can be registered and used to select the subtracted constant between 125 and 177 on the next clock cycle (using a 10 bit binary accumulator). Since in this case you will have more than two clock cycles between the counter rolling over it can be further pipelined with a register between the constant selection and the subtractor to allow the design to run at very high rates limited by the bit width of the subtractor.

You're right that would work, except that you don't ever reload the phase accumulator. Instead, you'd add 847 every time subtracting 125 would make it go negative, and toggle the output FF at each such occurrence. I suppose that's what you mean by 'reloading the adjusted value for the modulus'. Either way, it still 11 FFs and it makes no difference for the cycle-to-cycle phase errors. It's still a pattern that repeats every 12.5us.

Jeroen Belleman