PLL tricks

Well maybe he's not civil? I didn't see errors in it.. It's how you are perceiving it.

Jamie

And you keep coming back to bite more. I guess you like the taste!

I'll have to start calling you Chiwawa.

Wait, you snipped the part where you explained how to read the schematic and you said the gates are not connected to the sources. Use your rules and tell me what the source of the right hand FET is connected to...

On a sunny day (Wed, 17 Sep 2014 18:30:53 -0400) it happened rickman wrote in :

OK, you are an insulting clueless PIG. Now to the facts, in KINDERGARTEN kids (at least over here) learn to spell (dog, cat). later they recognize whole words. And a bit later they can read a page, a bit later again they can read a story, and a bit later grasp the 300 pages novel.

You are STUCK in spelling and endlessy moaning, cannot see the words, and of course not the diagram and the general meaning of the circuit it represents. You are an electrodislexic.

PLZ go to electronics.basics.for.dummies. And on top of that, your analog component knowledge is absent, JFETS do NOT make resistors with gate and source connected, look up the datasheet of the BF245, it is a penthode (you do not know about those either) and flat for voltages > 6 volt. So piss of, go back to connecting wires to logic gates. J.L. is right, you are a wste of time. Do not hold your breath for any replies, but I would not cry if you did.

Thank you for your courteous and thoughtful reply.

Do you mean Pentode? You are right, I don't know what a penthode [sic] is. However I do remember pentodes which are similar to FETs in their output characteristics. I seem to recall that the bipolar transistor has similar output characteristics to a triode.

That as it may, looking at the data sheet from NXP

Figure 20 shows that with the gate - source voltage at 0 the Rds is approximately 200 ohms depending on the exact version (A, B, C). Your circuit shows very low voltages from mV to the voltage needed to drive the LED. That is not 6 volt and is on the part of the output curve where the FET is relatively linear given the 0 volt Vgs. So why is that not a resistor?

The first problem I have in understanding your circuit is just knowing if I am reading the schematic correctly. Is the circuit such that all the sources except one are connected to all the gates, connected to the high voltage, low current side of the transformer. The low voltage and high current side of the transformer is connected to the one lone source. Is that correct?

You are right in that I am much more familiar with the digital side of things. That is why I am asking about your circuit. I would like to understand how it works. Obviously however the schematic is, it works, and I'm sure you have good reasons for designing it the way you did. That is what I'm curious about.

Not if the step size is one and there's a lastch before the DAC output

Or, if the increments are not of unit size, then a simple conditional subtractor is enough to handle the overflow. A no-brainer in VHDL. BCD is not required anywhere in this circuit -- as someone else said, a number is a number, so chose the simplest(i.e. binary) representation.

Which is an interesting phenomenon on its own. I see exactly the same behaviour in my professional field: the word "decimal" seems to be connected to "BCD" by an almost unbreakable mental link. It was a very enlightening experience to try to persuade an otherwise smart person that he doesn't need to perform calculations on his fractional number in BCD just to have decimal arithmetic rules (mostly rounding) and that the scaled binary integer format can emulate it much more efficiently. It is a primary-school-level calculus, but the hard part is to free your adversary from the mental chain of the BCD-related associations. :-)

Best regards, Piotr

If an N-bit DAC is doing the waveform reconstruction, though, the period has to be an integer multiple of 2**N clocks. That restricts the range of choices considerably.

Cheers

Phil Hobbs

Belay that, shipmates--blow me down for posting before me morning grog. (Er, coffee. 'Tis Pirate Day along o' the Fiji Isles.)

Cheers

Phil Hobbs

Am 17.09.2014 um 19:39 schrieb Kevin Aylward:

Ahmmm....

Sure, that will fit into an iPhone :-)

Maybe I have not explained sufficiently. To elaborate:

Kevin Aylward

As much as I would love to help you, I can't believe the lack of insight here.

Experienced people can see what the circuit is, even if there was some minor hand slip in the drawing, which I didn't see any btw.

Why not just give up beating the dead horse?

Jamie

If you can't explain such a simple circuit, I think I am not the only one who had a lack of insight... and a few other qualities.

Coffee obviously improves you considerably. Most of what you post is a few miles over my head, but I read that one and thought "Wait... That can't be right."

Me to. But I was nowhere near brave enough to say so. Phil Hobbs is almost always right, even if even the best of us slip up from time to time - search on "errors of action"

In the UK we called them "drop-offs" and a lot of engineering management is aimed at catching them early - by "walk-throughs" and "design reviews" when fixing them is cheap and easy, and before the satellite makes it's course correction half-way to Venus and gets the speed right and the direction as wrong as possible.

Right, but that's usually a later stage, isn't it?

To answer more directly, here's my process here--we already know (I think) that oscillator phase performance is limited by resonator Q and flicker noise in the BJT, and that crystals have the highest Q available in this frequency range.

Robert J. Matthys wrote extensively about VHF crystal oscillator design in RF Design in two articles in the '80s. (buried in my dungeon somewhere) IIRC, the jist of it was that very, very high performance was attainable at VHF using over-tone crystals, the trick being not to spoil the crystal's inherent Q, which most people do.

So, as a first approximation, we 'know' the lowest phase-noise solution is likely to involve a quartz crystal and the best transistor we can find.

We also know that multiplying up x1944 from 80KHz--essentially John's problem--is a mother (of invention), and that a lower multiplier would help a great deal on several fronts.

All of that qualitative logic led me to propose:

Reference Generator Master Oscillator .------------------------------. .------------------------. | VCXO | 720 | VCXO | | .---. .---. .---. .----. | KHz | .---. .---. .---. |

The reference generator's phase detector runs at 10MHz and its VCXO output is at least as good as the Master Oscillator's VCXO, so this block doesn't, to a first order, limit performance.

I believe it's a lot better than Kevin's passive multiplier because the crystal is so much better than any other [passive selection filter + amplifier] scheme. I think. Maybe Kevin will correct me.

So that's my typical stream-of-consciousness, birthed whilst jogging.

The next step is usually "Dang--fatal flaw--that won't work because..."

Computations come next, e.g., "Am I getting the theoretical performance from this crystal with this magnificent Q?"

If that weren't good enough I might also look at other high-factor multiplier topologies (such as those used for microwave sources) and evaluate them.

That's kind of what I did! (I made a constant-current SMPS that pre-charged the load's 0.1F input cap., then dropped a 500A short-protected MOSFET 'penny' into the 'fusebox.')

Cheers, James Arthur

Pretty neat that a 100g critter makes 15W. Also neat that going from

Now if we only had those figures for other species, we could compute the air speed velocity of a laden swallow. ("African or European swallow," you ask...)

Cheers, James Arthur

the Tour de France riders put around 6W/kg in the pedals all day, in the sprint the best can do around 22W/kg for a few seconds

-Lasse

It degrades it a bit. There are two phase detectors in series. There's nothing to stop John running a third phase detector at 80KHz (between the 155.52MHz VCXO and the external 10MHz and feeding that into the block you've labelled LPF which probably ought to include an integrator) and organising the system so that the third phase detector dominates the feedback to the 155.52MHZ VCXO at very low frequencies.

I tend to think that using a DDS or a fractional-N system with a product phase-detector at 10MHz is going to be simpler and cheaper than adding a second VCXO and PLL, and would probably work just as well - perhaps better, in the proportion 720kHz to 10MHz.

The second VCXO running at 90MHz is certainly a cute idea, if a touch extravagant.

John's opinions to the contrary, DDS outputs don't "jitter". They may have very small systematic phase fluctuations, but unless you are silly enough to feed them into a thoroughly non-linear bang-bang phase detector, they'll get low pass-filtered out - they should repeat at at least 80kHz in this instance, and that's a long way above the 500Hz

I would have thought that the passive multiplier would only have made sense if you wanted a master oscillator running at a couple of GHz to feed into something like an AD9915 from which you could derive better

If anybody still makes YIG-tuned GHz oscillators, I'd love to hear about it. I had couple of potential applications for these devices in the

Actually, I'm more puzzled about what an "air speed velocity" might be.

"Air speed" is a familiar term, and "flight velocity" might be one that a physicist might use, but the mixed term sounds odd.