PLL tricks

Sep 09, 2014 483 Replies

On a sunny day (Mon, 22 Sep 2014 07:39:27 -0700 (PDT)) it happened snipped-for-privacy@yahoo.com wrote in :

No, look at this:

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I think that is pretty much the circuit diagram of this one too.

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That website gives nice info, bottom page.

On a sunny day (Mon, 22 Sep 2014 08:20:34 -0700) it happened John Larkin wrote in :

Interesting, never seen those, or noticed those.

Yep.

The 'pucks' have a above them an adjustment screw, a bit like the screws for tuning in cavities, to get the exact frequency, not sure if those actually touch the ceramic:

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Those screws are under the red blurbs.

On a sunny day (Mon, 22 Sep 2014 07:39:27 -0700 (PDT)) it happened snipped-for-privacy@yahoo.com wrote in :

Well, maybe you are right, could be active FET mixer... then I will have to connect the coax a bit differently :-)

When ever I see really low noise, its a given that it uses lots of volts. You need the voltage swing to override circuit noise. My stuff is pretty much restricted to below 5V, with 3.3 being the main stay. This means 2.8V internal as everything is regulated. External power supplies are way too noisy. In fact, my BG has 20 times less supply current for the same noise offered by the likes of Linear Tech, Maxim, Analog Devices etc.

Digital control is a bit tricky, especially for the heated few ppb oscillators. 1 ppb steps would be way to large, so its usually all smooth analog

I got into it by default. The only reasonable option near to where I lived, when I anticipated the current job at the then current employer was not going to last.

I don't intend to stay in oscillators...

Indeed.

Kevin Aylward

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- SuperSpice

I remember them well. In fact I remember telling you about them and buying you a handful in S.F.--at Halted, was it?--1998 ;-) (For possible DDG use.)

Especially the low TC part. 1 GHz drifting 2ppm/C could get a little squirrely.

Yep.

I like the microwave brick-style SRD->schottky sampling phase detector--eliminates the need for one digital divider, and the need to square up the 155.52 MHz. That's slick.

I assume samplers can be low-jitter. They're used in sampling scopes, after all.

Cheers, James Arthur

We do make a couple of DDGs that use these as burst oscillators. They are OK for timing relatively short delays, in the hundreds of microseconds maybe. Longer delays need fancier schemes to keep the jitter down.

The bad thing about the coax resonators is that their Zo tends to be low, like 10 ohms maybe.

Samplers can have sub-ps jitter, but their equivalent noise figures are terrible. They also tend to have a lot of time jitter vs temperature. I think my d-flop bangbang phase detector will have the best time stability.

John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com

But logic is similar to what you do in that if you have a good innate sense of what is happening it helps you to see the shortcuts.

Even though the tools may do logic minimization, etc., there are still plenty of ways to optimize the logic at a high level without getting into Karnaugh maps and such. In essence you need to understand what is important and what is not. Just banging code and letting the tools work it out doesn't get you a good design any more than letting a compiler worry about your C code or letting a spice simulation tell you your circuit values. You have to know how to use the tools well to get good results.

Rick

Yeah, that has the advantage that you can sync it with an ECL D-flop and take out virtually any arbitrary drift, delay, or wiggle.

Sounds good.

I was trying to avoid the comparator noise from squaring up the

155.52MHz, but there doesn't seem to be any easy way.

It would save a lot in the signal path if you could phase compare sine waves, but with all these non-common factors in the frequencies the filtering's impossible.

So as Caesar the famous lunch salad inventor always said, divide, and conquer.

Cheers, James

The D-type bistable phase detector is a sampling detector. The signal at th e D-input only influences the output at the active edge of the clock wavefo rm.

If you don't think about what's going on.

Any product detector will let you get away with comparing two sine waves. A n AD834 might be one example.

Use a DDS to get a 10MHz sine wave out of the 155.52MHz oscillator - low-pa ss filter the 10MHz to get reduce of the 155.52MHz step artifacts. I suspec t that a two pole filter with a bit of ringing would distort the exponentia l segments between steps into something close enough to a sine wave for mos t purposes.

Detect phase with a reasonably linear product detector, so that the residua l - systematic - spurs can average out over the 12.5usec repeat cycle of th e 10MHz/155.52MHz mix. John wants a roughly 500Hz of bandwidth in his PLL, so there's plenty of room for a bunch of poles of low-pass filtering of the phase detector output.

And get assassinated on the Ides of March?

Bill Sloman, Sydney

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the D-input only influences the output at the active edge of the clock wave form.

The topic instant was schottky analog samplers.

An AD834 might be one example.

If John has to divide down f(ref) and f(out), neither are sine waves. One appeal of a sampler was that it eliminates the f(out) comparator and divider.

If you mix 10Mhz and 155.52MHz sines directly, the result is an unfilterabl e mess.

pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I susp ect that a two pole filter with a bit of ringing would distort the exponent ial segments between steps into something close enough to a sine wave for m ost purposes.

ual - systematic - spurs can average out over the 12.5usec repeat c...

The DDS in the signal path adds a horrendous, variable delay, loads of transistors in the signal path, and no control over how clean the supplies and signals are. I don't see how the DDS' wandering analog output delay can be re-sync'd to the reference clock, something the bang-bang can do with a single flop.

A DDS outputs a stepped pseudo-sine with a zero-crossing that will periodically coincide with flat spots on the DDS'output waveform, which modulates the zero-cross time (unless specific steps are taken to prevent it). Filtering the DDS output to remove this problem adds more critical circuitry, delay and drift.

Analog multiplier phase detectors are duty-cycle, d.c. offset, and amplitude sensitive, all of which seem like bad ideas when John needs rock-solid phase stability, AIUI.

Adding a DDS comes with a lot of deficits.

Cheers, James Arthur

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t the D-input only influences the output at the active edge of the clock wa veform.

But the defects of the sampling detector aren't specific to the technology used to realise it.

s. An AD834 might be one example.

But the output from a DDS is a good approximation to a sine wave, and the s purs injected by the DDS process are deterministic, small and repeat at 80k Hz.

ble

What's that got to do with anything? If you use a DDS clocked by the 155.52 MHz source to create a good approximation to a sine wave, and compare it wi th yur reference 10MHz with a product-type phase detector - the AD834 would be an overkill, but it would work - the output contains the usual 20MHz co ntent, which you can filter - as has been done in PLL for as long as they h ave existed.

It's certainly not an unfilterable mess, and if you think that you aren't t hinking straight. Drink some coffee and re-energise your brain.

w-pass filter the 10MHz to get reduce of the 155.52MHz step artifacts. I su spect that a two pole filter with a bit of ringing would distort the expone ntial segments between steps into something close enough to a sine wave for most purposes.

idual - systematic - spurs can average out over the 12.5usec repeat cycle o f the 10MHz/155.52MHz mix. John wants a roughly 500Hz of bandwidth in his P LL, so there's plenty of room for a bunch of poles of low-pass filtering of the phase detector output.

The DDS would use the 155.52MHz source to clock the DAC producing the stair

-case approximation to the desired 10MHz waveform.

That's not any kind of "horrendous variable delay" and there are very few t ransistors in that signal path. And you've got total control over rails fee ding the DDS chip. The DDS doesn't have any kind of "wandering analog outpu t delay". You are as bad as John Larkin, who claimed that the DDS output "j ittered" when it has - at worst - perfectly systematic, and small, deviatio ns from the desired sine wave.

My guess is that the - obligatory - low pass filter on the output of the DD S should be a slightly peaky two-pole with a 3dB point at about 78MHz. It n ecessarily adds delay, but the drift on the 13nsec of delay involved can be kept within bounds by an intelligent choice of components.

They do need careful analog design, which John does claim that he can deliv er. They do have the overwhelming advantage over the bang-bang phase detector t hat John seems to fancy - because he got one to work, once when he could sa mple at 77Mz - in that they average over the complete cycle rather than loo king within a very narrow window, and throwing away loads of useful informa tion that shows up outside that window.

But nowhere near as many - or as severe - deficits as you seem to imagine. I won't say "as you seem to think" because you really don't seem to have th ought all that hard about what's involved.

Design is all about compromises, and they rarely work out to be identical f rom one design to the next.

Bill Sloman, Sydney

I liked the idea that if you have the amount of power that comes out of a standard USB port, you can fly.

It's almost like they're really aerodynamic or something. :)

As a special added bonus, if you have two of them of the correct configurations, they can *manufacture copies of themselves* at the rate of three or four a year.

She don't lie, she don't lie, she don't lie...

Matt Roberds

euromillions.

Well modern electronix is vastly more sensitive to radiation and Single Event Upsets. Not a smart idea in a device full of radioactive materials.

?-/

On a sunny day (Mon, 22 Sep 2014 17:48:11 -0700 (PDT)) it happened snipped-for-privacy@yahoo.com wrote in :

Just use the sum or difference, easy to filter. Either 165.52 or 145.52 MHz Any ol' radio does that.

Ahh, multiple input amps--a diversity receiver, or more likely two feedhorns for two bands. I should have thought of that.

(Looking back at your board photo it's the latter, indicated by the different geometries of the two input amps' structures.)

Two DROs, gated for band-switching as suspected.

That's a pretty impressive mixer, running at Ku-band.

Nice stuff. The DROs use BJTs--pretty neat that that's possible nowadays.

Cheers, James Arthur

On a sunny day (Tue, 23 Sep 2014 05:02:56 -0700 (PDT)) it happened snipped-for-privacy@yahoo.com wrote in :

No, look again, one amp is vertical polarization, the other horizontal. One horn.

Yes I have some of those 2SC5508, Ft >= 20 GHz, noise typical 1.1 dB :-)

Normally I'd expect the hair-pin bandpass to be the IF filter. I can't tell from the dimensions from here, but it looks like it's at r.f. rather than i.f. Weird.

ISTM the last FET to the right is the mixer, fed hot from the DROs, which then goes through a wimpy IF filter before heading to the output amp.

I don't see any path from the DROs to the output chip, so either I've missed it or it's likely not a mixer, just an amp.

As noted before, a Ku-band mixer chip would be something *mighty* special.

Cheers, James Arthur

You're serving a very valuable application area. Lots of people don't have

15v supplies and 8 peak watts to burn, or space for a big metal brick to call home.

Classy.

My notion was ramp-and-hold stuff, which should have been somewhat clean. I was mostly after 1ppm or 0.5ppm over temperature for an spread spectrum transmitter, not ultimate world-besting performance.

They were making millions of something I designed, and an upgraded crystal would've made possible a large improvement.

Nothing wrong with it, not at all. You've done some very nice work. I just realized at the time that I didn't own an oscillator company and didn't feel like starting one.

Doing the same work, working *for an oscillator company* would've been completely different (and lots of fun).

Cheers,

James Arthur

  1. Not to ppb.
  2. We're trying to extract an 80KHz phase signal / beat frequency.

Or, more specifically, to fix the 155.52 MHz phase in place, at 15.552 000 00 cycles per 10MHz cycle, to a few pS over some undefined time interval.

Cheers, James Arthur

AIUI the object is to stabilize the phase of the 155.52MHz output to ~10ppm w.r.t. a precision 10MHz reference signal.

When you insert the DDS between the output signal and the phase comparison, you've added an uncalibrated delay that cannot be removed, ditto any noise or jitter produced in the DDS, that's my point.

Cheers, James Arthur

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