Low jitter transmission of LVDS signals

"The Journey is the reward"

eff.com

don't know about your low smoke requirement, but look at Belden 1800F I believe it's Zc = 110 ohms

How low do you want the added jitter to be?

A 100 ohm shielded pair with a braid or drain, grounded on both ends, should be pretty good. Use a fast driver and an LVDS receiver with a symmetric threshold, not one with a big deliberate offset. I'm partial to FIN1101, a real screamer.

Use fat gauge (22-26) wire to minimize hf losses, which will cause deterministic jitter if you are transmitting data.

We've been piping PCI Ecpress over cable, similar situation, 2.5 GBPS per pair. We're seeing excellent eye diagrams over 7 meter cables between chassis on the bench.

Note that FIN1101, at 80 cents and 1.1 ns, is a better comparator than most.

Not completely sure at the moment, but I think it has to be < 10ps for the added noise to be < 1 lsb. The source oscillator is claimed to have < 1ps jitter, so it should be negligible, but it's going through some logic too. It's a delta-sigma clock.

Nice part, any reason not to standardize on it, other than a slight cost premium? No problems with ESD?

I'm using ye olde SN65LVDS parts which I think are symmetric.

deterministic

Logic? FPGAs are nasty for jitter. CMOS is mediocre. ECL, like EclipsLite, is great.

be

threshold,

Not that I've noticed. We sometimes use them for customer trigger input comparators with no added ESD protection.

Some LVDS parts have as much as 100 mv of deliberate offset.

deterministic

pair.

be

threshold,

I'm sure happy to hear that Larkin likes my chip work... I did that one in April 2001. ...Jim Thompson

Have you checked National's LVDS Owner's Manual? Total jitter will depend on the length of cable too. Their measurements are way out of line with your objective.

the length of cable too. Their measurements are way out of line with your objective.

Cable attenuation will cause "deterministic jitter" when data patterns are being transmitted. A continuous clock is less sensitive to attenuation because it gets only "random jitter."

There's also the distinction between "jitter" and "wander", the concept being that you have to pick some time span over which to measure jitter. Wander includes the slow stuff, like thermal effects on prop delay. The telecom people usually use 0.1 seconds as the cutover point.

be

threshold,

screamer.

Another year and it'll be a teenager. :)

should be

threshold,

screamer.

Like me, I recently turned 18-1/4 >:-} ...Jim Thompson

the length of cable too. Their measurements are way out of line with your objective.

True, but if he runs it any distance, attenuation causes his transition times to suffer putting him back to a humdrum 20-50ps RMS jitter just due to the comparator at the receiving end, and these signals are smallish.

the length of cable too. Their measurements are way out of line with your objective.

to suffer putting him back to a humdrum 20-50ps RMS jitter just due to the comparator at the receiving end, and these signals are smallish.

At one meter, a couple ps RMS should be easy. We trigger sampling scopes over a meter or two of coax and get down there, ground loops and all. LVDS over a diff pair should be better.

ECL is current-steering logic, and ECL power rails have much less "grass" than rails feeding CMOS and other voltage-switching logic. Noise on the power rails feeds into the comparator that is detecting the edges (Power Supply Rejection Ratios - PSRRs - are lousy at high frequencies) This shifts the point where the comparator thinks that the in-phase and anti-phase inputs have crossed over and thus introduces jitter.

From an analog design point of view, jitter is the voltage noise on the cross-over point projected onto the edge speed of the two signals being compared. The less dispersive your cable, the better the edge speed at the receiver end and the lower the jitter.

hould be

reshold,

reamer.

Wow, you could not have scripted that better if you had tried.

should be

threshold,

screamer.

He has mentioned that before. As I recall, he said he did only part of the chip, the "analog" front end. Other than bragging, he hasn't been helpful as regards details, even performance. We've done a fair amount of characterization of the FIN1101 and other LVDS parts, to learn stuff that's not on the data sheets. Some of these parts make great laser drivers.

There's little doubt that, by now, we've made a lot more money off FIN1101s than he has.

That is a great comeback

Pity he has killfiled me, and misses all my great lines.

He does whine about the stuff that I don't post, which he can't see... because he's killfiled me!

on the length of cable too. Their measurements are way out of line with your objective.

to suffer putting him back to a humdrum 20-50ps RMS jitter just due to the comparator at the receiving end, and these signals are smallish.

Okay, 1 m I can believe, missed that part in the OP.

should be

threshold,

screamer.

Sure, but you were always slow. ;-)

for

gh

ds, should be

ic threshold,

al screamer.

at

My knee jerk reaction is to support a balance budget amendment, however, I believe that if it were implemented the budget would get balanced by never cutting spending (actually increasing it) and forever raising taxes because it is "constitutionally " required. It is better for the government to be insolvent.