Starting with LVDS

Frank, be serious: You do not tell us which FPGA family and which board. You don't report that you have tried a different output standard. You mention little about your design and environment. How can you possibly expect any meaningful help? It's like calling a doctor: "What should I do, it hurts!" Peter Alfke

Frank, be serious: You do not tell us which FPGA family and which board. You don't report that you have tried a different output standard. You mention little about your design and environment. How can you possibly expect any meaningful help? It's like calling a doctor: "What should I do, it hurts!" Peter Alfke

"Frank Schreiber" schrieb im Newsbeitrag news:dr0fec$kvu$ snipped-for-privacy@anderson.hrz.tu-chemnitz.de...

Maxim, ADI and TI LVDS DACs all require LVDS clock to latch the data, unless you provide some meaningful data on the output and suitable clock do not expect anything.

you said "assume" all wires and DAC are working, well assuming that all should work as long as you made some meaningful (as per DAC datasheet spec) singals on the LVDS data and clock outputs.

Antti

Frank

Remember to check the scale on your oscilloscpe. The LVDS signal is very small and easy to miss if setup for something like TTL levels. I've done that before myself. If you are using Xilinx you can check if LVDS is implemented from the pin file I think or do it my favorite way in by looking at the design in FPGA editor.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

Hi John,

he is looking at DAC output not at LVDS signals. he said assume the wires __and__ DAC are working properly, so hes oscilloscope is on the output of an LVDS DAC

Antti

"John Adair" schrieb im Newsbeitrag news:dr0oor$gck$ snipped-for-privacy@newsg2.svr.pol.co.uk...

Not entirely clear to me that he is looking at the DAC output from those words. Didn't even say that the oscilloscpe was actually connected never mind what to.

Frank give us all a bit more info. We might be assuming something or nothing correctly. The old swing on the tree graphic is coming to mind.

John Adair Enterpoint Ltd. - We're at DATE2006. Come and say hello.

Dear all, I am using Virtex 4 from Xillinx, and I really missed the clock for LVDS. So, should I transfer data to LVDS each time posedge of the clock. The clock should be LVDS clock, LTTL clock or any clock is possible. Many thanks Frank

unless

spec)

"Frank Schreiber" schrieb im Newsbeitrag news:dr25fb$ii6$ snipped-for-privacy@anderson.hrz.tu-chemnitz.de...

think of LVDS that you use 2 wires an not 1 for 1 signal

for LVDS its irrelevant if the signal is clock or data or whatever

what I said is that if you have DAC chip that uses LVDS standard then this DAC chip does need a LVDS clock to latch the data, but its only my guess, you really did not provide enough info.

So, in this case should I provide 8 bits for data, and 1 bits for clock ? Any clock else ? Frank

"Frank Schreiber" schrieb im Newsbeitrag news:dr26uq$n0i$ snipped-for-privacy@anderson.hrz.tu-chemnitz.de...

if you have a DAC chip with 8 bit DDR LVDS then you have 8 bit data in FPGA and 1 bit clock, and there will be 16 actual data wires(8 +- pairs)) from FPGA and 2 clock lines (1 +- pair)

but you can not expect to get help if you dont say what is the thing that is connnected to FPGA, I assume its an high speed digital analog converter, but only you know it for sure, others can only guess

Are you trying to implement the transmitter within the FPGA?

I don't understand you Frank! Multiple times others have explained to you that if you don't give sufficient information, it is IMPOSSIBLE to answer your questions.

Give the following information, and maybe you can be helped:

2) What EXACT device (part number) are you connecting it to

4) Bonus info would be the manufacturer of the board (or if it is your own design, some more details of the design and the purpose), the clock rate you are trying to use, whether the data is single or double data rate.

Philip Freidin Fliptronics