Hi there,
I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my FPGA. The FPGA features 2 LVDS interfaces, whereas each LVDS pair is located at opposite sides of the device, meaning there will be some extensive routing to do. I designed a resistor network for the level conversion from LVPECL to LVDS. What I'd like to know now is a) Can I route the 2x2 lines (two times differential to the two opposite sides of the FPGA) one-to-one out of my clock device to the inputs or should I use a dedicated buffer / repeater IC for clock distribution? b) If clock buffer are needed, should I use LVPECL buffers and do the conversion to LVDS level afterwards or should I perfom the conversion before the buffer and then use an LVDS IC? c) Where should I place the level conversion network? Is is better to place it right at the LVPECL output or is it more advisable to do it right before the FPGA inputs after a transmission line length of about 7 cm? Any help, comments, advice is highly appreciated!
Thank you all very much. Kurt