EL7900

Yes. that's up my alley. Thanks for reminding me.

Jamie

I like skinny girls. Tastes vary, and nature provides.

I tried 0xFFFF.com in my browser, and it did strange things.

On Wed, 5 Sep 2012 10:57:30 -0700 (PDT), Bill Sloman wrote:

--- From my point of view there's not much inspiration required to fulfill the generally mundane requests for help around here, although a few have tickled my fancy and resulted in interesting solutions.

Here's one for a 3 phase generator:

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SYMATTR InstName V1 SYMBOL cap -2096 240 R90 WINDOW 0 -33 25 VBottom 2 WINDOW 3 -33 27 VTop 2 SYMATTR InstName C1 SYMATTR Value 100nF SYMBOL res -2064 304 R90 WINDOW 0 68 58 VBottom 2 WINDOW 3 71 58 VTop 2 SYMATTR InstName R1 SYMATTR Value 100k SYMBOL Digital\\dflop -1600 48 R0 WINDOW 3 8 168 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 3 vlow -3 SYMATTR InstName A2 SYMBOL Digital\\dflop -1376 48 R0 WINDOW 3 8 168 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 3 vlow -3 SYMATTR InstName A3 SYMBOL Digital\\dflop -1088 48 R0 WINDOW 3 8 168 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 3 vlow -3 SYMATTR InstName A4 SYMBOL Digital\\dflop -864 48 R0 WINDOW 3 8 168 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 3 vlow -3 SYMATTR InstName A5 SYMBOL cap 48 608 R0 WINDOW 0 -41 34 Left 2 WINDOW 3 -88 65 Left 2 SYMATTR InstName C7 SYMATTR Value 11nF SYMBOL cap -80 496 R0 WINDOW 0 -55 -2 Left 2 WINDOW 3 -87 35 Left 2 SYMATTR InstName C8 SYMATTR Value 22nF SYMBOL res -80 576 R90 WINDOW 0 65 62 VBottom 2 WINDOW 3 70 60 VTop 2 SYMATTR InstName R7 SYMATTR Value 1meg SYMBOL res 64 576 R90 WINDOW 0 -30 53 VBottom 2 WINDOW 3 -28 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1meg SYMBOL cap 48 128 R0 WINDOW 0 -41 34 Left 2 WINDOW 3 -88 65 Left 2 SYMATTR InstName C2 SYMATTR Value 11nF SYMBOL cap -80 16 R0 WINDOW 0 -55 -2 Left 2 WINDOW 3 -87 35 Left 2 SYMATTR InstName C3 SYMATTR Value 22nF SYMBOL res -384 80 R90 WINDOW 0 -30 60 VBottom 2 WINDOW 3 -27 57 VTop 2 SYMATTR InstName R2 SYMATTR Value 100k SYMBOL res 64 96 R90 WINDOW 0 -30 53 VBottom 2 WINDOW 3 -28 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 1meg SYMBOL cap 48 -304 R0 WINDOW 0 -41 34 Left 2 WINDOW 3 -88 65 Left 2 SYMATTR InstName C4 SYMATTR Value 11nF SYMBOL cap -80 -416 R0 WINDOW 0 -55 -2 Left 2 WINDOW 3 -87 35 Left 2 SYMATTR InstName C5 SYMATTR Value 22nF SYMBOL res -80 -336 R90 WINDOW 0 65 62 VBottom 2 WINDOW 3 70 60 VTop 2 SYMATTR InstName R4 SYMATTR Value 1meg SYMBOL res 64 -336 R90 WINDOW 0 -30 53 VBottom 2 WINDOW 3 -28 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 1meg SYMBOL Opamps\\LT1677 112 32 R0 SYMATTR InstName U1 SYMBOL res 240 112 R0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res 240 592 R0 SYMATTR InstName R9 SYMATTR Value 1k SYMBOL res 240 -320 R0 SYMATTR InstName R10 SYMATTR Value 1k SYMBOL Opamps\\LT1677 112 512 R0 SYMATTR InstName U2 SYMBOL Opamps\\LT1677 112 -400 R0 SYMATTR InstName U3 SYMBOL res -384 208 R90 WINDOW 0 -38 60 VBottom 2 WINDOW 3 -30 62 VTop 2 SYMATTR InstName R11 SYMATTR Value 300k SYMBOL Digital\\dflop -640 128 R0 WINDOW 3 8 168 Invisible 2 SYMATTR Value trise 1e-7 tfall 1e-7 vhigh 3 vlow -3 SYMATTR InstName A6 SYMBOL res -80 96 R90 WINDOW 0 65 62 VBottom 2 WINDOW 3 70 60 VTop 2 SYMATTR InstName R12 SYMATTR Value 1meg SYMBOL Opamps\\LT1677 -272 48 R0 SYMATTR InstName U4 SYMBOL cap -256 0 R90 WINDOW 0 -32 36 VBottom 2 WINDOW 3 -31 29 VTop 2 SYMATTR InstName C6 SYMATTR Value 220nF SYMBOL res -224 -96 R90 WINDOW 0 -32 64 VBottom 2 WINDOW 3 -32 67 VTop 2 SYMATTR InstName R13 SYMATTR Value 1meg SYMBOL Opamps\\LT1677 -272 528 R0 SYMATTR InstName U5 SYMBOL cap -240 464 R90 WINDOW 0 -34 37 VBottom 2 WINDOW 3 -36 30 VTop 2 SYMATTR InstName C9 SYMATTR Value 220nF SYMBOL res -224 368 R90 WINDOW 0 -47 62 VBottom 2 WINDOW 3 -37 62 VTop 2 SYMATTR InstName R14 SYMATTR Value 1meg SYMBOL Opamps\\LT1677 -272 -384 R0 SYMATTR InstName U6 SYMBOL cap -240 -448 R90 WINDOW 0 -37 34 VBottom 2 WINDOW 3 -33 30 VTop 2 SYMATTR InstName C10 SYMATTR Value 220nF SYMBOL res -384 368 R90 WINDOW 0 -30 51 VBottom 2 WINDOW 3 -29 51 VTop 2 SYMATTR InstName R17 SYMATTR Value 100k SYMBOL res -384 -448 R90 WINDOW 0 -37 62 VBottom 2 WINDOW 3 -36 63 VTop 2 SYMATTR InstName R18 SYMATTR Value 100k SYMBOL res -224 -544 R90 WINDOW 0 -47 62 VBottom 2 WINDOW 3 -37 62 VTop 2 SYMATTR InstName R19 SYMATTR Value 1meg SYMBOL res -384 560 R90 WINDOW 0 65 62 VBottom 2 WINDOW 3 70 60 VTop 2 SYMATTR InstName R15 SYMATTR Value 300k SYMBOL res -384 -352 R90 WINDOW 0 65 62 VBottom 2 WINDOW 3 70 60 VTop 2 SYMATTR InstName R16 SYMATTR Value 300k SYMBOL voltage -2304 384 R0 WINDOW 0 111 105 Left 2 WINDOW 3 24 96 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value 3 SYMBOL voltage -2208 496 R180 WINDOW 0 53 7 Left 2 WINDOW 3 24 16 Invisible 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 3 TEXT -2384 552 Left 2 !.tran 0 1s 0 1ms startup uic TEXT -2376 584 Left 2 !;ac oct 128 1 100 TEXT 320 -336 Left 2 ;>PHASE 1 TEXT 320 576 Left 2 ;>PHASE 2 TEXT 320 96 Left 2 ;>PHASE 3

---

--- Critique, please?

---

--- Count Larkin out?

-- JF

T'weren't supposed to be "poetry" you fool.

?-)

The async clear looks to have logic hazards.

Right, it's doggerel.

"Inept handling of subject"

Back to your favorite subject again, JackScat?

Do f*ck-off now, there's a good boy.

Well,

It depends on a very fast power supply rise

It violates the chip edge rate specs

If the clock is async to the clear, flipflop states can get scrambled and it won't work. That would be a low-probability intermittent startup bug.

Is there another reset problem?

The filters could use a little tuning too, maybe. I like to use FilterPro for quick active filter designs.

"Maybe"? Bwahahahahahaha ;-)

For such simple Sallen-Key?? ...Jim Thompson

I was being polite. You wouldn't understand.

Sure. FilterPro will take into account opamp GBW and pick standard parts values, and plot the resulting real-world filters, in maybe 1% of the time it would take to do by hand. What's not to like about that?

The NuHertz software is even better, but it's expensive. We have their passive filter version, which has paid for itself 10x or more by now.

Oh, it's not literally Sallen-Key, because the first stage inverts.

Sallen-Key is one OpAmp stage at a time. But's it's generally crap. I avoid them except for the most simplistic slop. Having to tweak for GBW is NOT what _I_ call engineering... since I have to design for repeated manufacturability with _NO_ tweaks. ...Jim Thompson

I use them a lot because the DC gain can be made exactly 1, and doesn't depend on resistor values or resistor TCs. That's important when you want an entire measurement/digitizer chain to hold 50 PPM accuracy.

Tweak? FilterPro takes the opamp GBW into account in calculating the response. If you want to make a multi-MHz filter, you can account for opamp GBW in the design, or buy GHz opamps, or ignore GBW and get whatever happens. You prefer to ignore opamp phase shifts?

I use structures that are highly tolerant of OpAmp GBW... so are quite predictable.

The curious are referred to my many years earlier posts of normalized "p+1" filters... which suck up problems with capacitor dissipation factor and also allow freely placeable zeroes as well ;-)

But, what would I know, I've only been producing manufacturable active filters since ~1970... applying the techniques to be found in Herrero and Willoner. ...Jim Thompson

Not quite, it is handling of inept subject.

?-)

It's better to put in a Schmitt trigger, to get away from the actual supply rise-time.

Since it's LTSpice's generic D-tyoe bistable, that was a silly statement. Most are shift registers are designed so that the lag from the clock to the output is long enough to satisfy the input set-up time constraint on the inputs, but it can be a trap if you are making up the shift register from separate bistables.

It doesn't need a timing diagram. There are clock to output propagation delays and clear to output propagation delays. If the clock and the clear edge occur close enough together that you don't know which one will determine the output, you've got a race condition and you won't know how the outputs will come out.

Since you haven't got a lot of states for the three-element shift register to adopt, I can't quite see what John Larkin is anxious about at the system design level, but a careful designer would have used an extra bistable to synch the clear to the clock.

I've got a strop preference for using a smidgin of gain in Sallen and Keyes sections which can take it, and yours certainly can.

You specify 11nF capacitors at C2, C4 and C7, which are a swine to buy. With a bit of gain, you can use identical capacitors to the ones at C3, C5 and C8 (which will all then come from the same batch, reducing the need to pay for expensive close tolerance capacitors) and adjust the shape of the frequency response with resistors off the E96 grid.

It's not as bad as your poetry, but more Jim Thompson than Bob Widlar.

-- Bill Sloman, Nijmegen

If you build it from real parts, not imaginary ideal flops, real parts have input rate specs.

You refuse to ever see hairball async logic hazards.

No. No point to doing it.

Well, keep it to yourself.

Get Don Lancaster's Active Filter Cookbook, or download FilterPro.