I have a SMT338 board. This is a FPGA module and now I want to add a DDR SDRAM to my system. I have the ucf file provided by the company but in this file I don't find ddr_feedback clock. What it means?. I suppose that this pin is neccesary, but there is no pin called "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" y "ckn" but these signals are used by the fpga to the ddr.
Has anyone the solution?.
Regards
there are different IP cores, some use the extra feedback pin some dont.
boards that have the extra pin are better as they are easier to work with.
if you happen to have a board with no feedback pin then you need either use IP core that does not utilize the feedback, or make some workaround to the existing IP core so you can still use it.
Antti
Do you know for some core without feedback?.
please look
opb_mch_sdram
DS492.PDF page 7
connect to... what But I have to use a DDR core.
I'm curious,you have a sundance product, but haven't asked sundance for the answer.....
Who has said that I haven't asked sundance for the answer?.
The extra pin is used for DCM feedback which compensates logic delay. It is connected to the same DDR in as clk. For more info about clocking variations see the OPB_DDR (or PLB_DDR) datasheet.
Cheers,
guru
So, are you telling me that these two entries (of the ucf file used by edk) are the same?
Net fpga_0_MT46V16M16TG_DDR_CLK_FB LOC=; Net fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk_pin LOC=;
And this means that I have to change the following line (of the mhs file; hardware description) and put "DIR = IO " (because dcm needs a feedback signal).
PORT fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk_pin = fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk, DIR = O
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