No it does not. The OR gate locks up to a hard Hi O/P 1 then when the O/P goes to Lo the gate gets a hard "0" via the feed-back Cap.
The OP revised his conditions, and said bounce settles in a fixed time, that my circuit will adjust to by a variation of the Cap. Any logarithmic ringing below the Hi threshhold is ignored, (~ 2/3 Vcc). Regards Ken
But it's an OR gate.
CRAP .or. 0 = CRAP
John
D from BC snipped-for-privacy@comic.com posted to sci.electronics.design:
OK here is my suggestion:
5k 20 pF || ___ .-||-o-----|___|- 5v | || | | | __ .-o-----. __ gnd --\\ \\| .-------------------| \\ | | | | )o- o--------o/__/| | .---|__/ | __ | | | | '-------| \\ | | | | | )o-----o | 9602 | )---------------)---' '--|__/ | | | | | | | | | '--o----' | | | | | | | | '--+ +---' | | | | \\ / | | | | X | '--------------------| | / \\ | | | .--+ +---. | | | | | | | | | | | 5k | | | __ | | 20 pF || ___ | | '--| \\ | | .-||-.-----|___|- 5v | | | )o--' | | || | | | '-----|__/ | | | | | | | __ .-------. | | | '----\\ \\| | __ | | | | | o-------| \\ | | | 5v --o/__/| | | )o--)---)--------' | | .--|__/ | | | | | | | | | | | | 9602 | '----)----------' | '--o----' | | | | | | | | ----------o--------------'(created by AACircuit v1.28.6 beta 04/19/05
Now if someone wants to breadboard it or simulate it in spice i would like to see the results.
That's the classic approach. IIRC there is a version that somehow gets both positive and negative edge triggers from a single 9602.
I also don't know if the 9602 can handle the fast edges that "D from BC" mentions.
...Jim Thompson
The lower the tp ...the more I can increase the frequency in my app.
I suspect the cleanest approach would be two D-flops that catch the first occurrence of a transition (positive or negative) and cross-lock in some fashion to accomplish the "blanking interval"... neither one having to try to follow the vigorous ringing.
...Jim Thompson
A fast input spike can fire both one-shots! Then the fun begins.
John
If I have this right...
4 device delays for neg edge. 4 device delays for pos edge.IIRC, the JL cct only has a 2 device delay.
D from BC
My thoughts....
make a flip-flop that can alternately be positive- or negative-edge triggered, by adding XOR in front of clock input and tying one XOR input back to output.
BUT... DELAY switch-over to avoid racing.
My 74HC74 model indicates it can't cope with 20ns/20ns noise, so faster logic is needed.
Timings, etc., for illustration only... squeeze to fit ;-)
...Jim Thompson
Hey... that looks good. :) It looks like a hairballized spin off of JFs circuit. Still with 2 gate tp. Impressive.... :)
One detail I'm wondering about... You have Pre and Clr connected together for a system reset. Shouldn't one or the other be used..Not both..
D from BC
Yep, Just spotted that myself ;-)
...Jim Thompson
I think you can eliminate the HC04 by using Qbar of the ff.
John
Actually, just pull them high. There's really no powerup preference for either state.
John
I don't know. BOTH the clock flip AND the D-input need delay... otherwise SUAH timings are violated and the 74HC74 has "arrhythmia" ;-)
...Jim Thompson
It's only a simulation convenience.
...Jim Thompson
John Larkin snipped-for-privacy@highNOTlandTHIStechnologyPART.com posted to sci.electronics.design:
Though i did not design it that way, i could certainly translate the design into the fuse patterns at the time. I expect i could still do it today. Not that i would want to.
John Larkin snipped-for-privacy@highNOTlandTHIStechnologyPART.com posted to sci.electronics.design:
I finally managed to post one. Decided on 20 pF instead.
Input ------>
OR ====> o/p ----> | |__________ | | cap | ground
Regards Ken
John Larkin snipped-for-privacy@highNOTlandTHIStechnologyPART.com posted to sci.electronics.design:
Maybe, they are cross interlocked.
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