Debouncing....at About 1Mhz

Are you sure the word you want is "jitter"? Once an edge is detected, there's nothing until the corresponding next opposite edge, right? The word jitter describes a periodic time uncertainty for when an edge will arrive, not what happens immediately after the edge arrives. If in fact you're worried about "bounce" or additional transitions in the 100ns after an edge, that's not called jitter. It's a type of digital noise.

Anyway, if you add an XOR gate to your mix of available pieces, you'll be able to find a simple solution allowing the use of only a single oneshot delay element. But I might point out that most oneshot ICs come as dual parts. You may get a lower chip count by using two timers. BTW, there's a simple way to adjust the delay of two oneshots with one trimpot or external panel pot. It could even be a 10-turn precision pot with a turns-counting dial.

It would be simpler to learn how to terminate your signals properly.

Looks like you can do it with a dflop, a quad xor, and an RC.

Run the input through a delay-line edge detector (three gates of delay, then xor) and clock the dflop. Then rc lowpass the input and apply it to D. Q is the output.

John

Yeah...jitter is probably the wrong word.. I thought of jitter as some interval of spurious digital behavior. I'll read up on:

One shots ICs and xors...neato! I've haven't thought about that yet. :) I'll give it a shot (

Are you thinking reflection?

The source signal is from pcb power section with high di/dt and dv/dt.

D from BC

Seems to me that you could do it with a D flop, and two RC nets from Q to R and /Q to S to hard-hold it high or low for a tenth of a usec.

Jim

Ahhhhh........... :)

I'll try drawing it while stuck in traffic...

Thanks..

D from BC

What's all that ??? about?

John

Right, so the xor plus the dflop clock to output needs to have less delay than that... should be easy with fast parts. The xor is just to get the same polarity clock pulse from each (leading) clock edge. The d input is RC delayed, so you capture the "old" level; thus you take Q- not as the output. RC must be long enough to get past the multiple transitions at each edge. In fact, you could do it, I think, with an SR f/f (cross-coupled NANDs) driven from a similar xor nanded with RC- filtered clock...

Cheers, Tom

Or this.

Total delay is 1 xor plus the dflop. 5 ns shouldn't be hard with decent cmos parts.

John

It is not.

John

oh nooo.. I rushed another post and again left out details...

Ton can vary up to 0.5uS.. (Ton is the 0.5uS time in my ascii drawing.) The circuit should at least function between 100khz and 1Mhz. The only thing that is constant is the bounce time of about 0.1uS.

Was that one shot idea based on constant Ton? Or variable Ton?

D from BC

Ideally..edge A is transparent through the circuit. Ideally. edge B is transparent through the circuit. But no no no...everything takes time and I have to allow a max delay.

I have a timing budget of around 10nS for A to A' and B to B'. This circuit is being inserted in a chain . All the delays are adding up.. :(

By the way.. I just made up the A and A' nomenclature... Reserved? I do try to express problems in some way to be clear and simple.

D from BC