Debouncing....at About 1Mhz

D from BC snipped-for-privacy@comic.com posted to sci.electronics.design:

No, not really, just different.

Because the OP suggested there is a lot of other stuff in the whole circuit. Or, if you don't like that answer, "because I like working with small parts under a microscope." ;-) Though even better, because I can re-program it with JTAG in-circuit, using the same programming pod I use for many other parts.

Cheers, Tom

You can't tell whether an apostrophe would be required without the remainder of the sentence. What he wrote was:

So, the question is whether your surname is "Fields" (plural) or "Field's" (possessive); I shall assume the former, as I don't see any apostrophe in your "From" header.

His use of your surname in that sentence wasn't posssesive. And if it was, the abbreviation should have been "JFs'" with a trailing apostrophe (plural possessive).

And have less EMI, right?

It will probably screw up, maybe even lock up, now and then. And you can't prove, or even be confident, that it won't. Simulating a circuit like this with a clean simulated edge bounce is naiive; in real life, all weird timings are possible, and the circuit itself will have part tolerances, temperature changes, and signal history (stored in the various ghastly RC glitch circuits) in a literally infinite set of combinations. It's crap.

Since you seem enamored of this complex mess, I have little more to say.

John

So what happens when a really fast spike fires both one-shots? What happens when an edge comes in just about the time one or both one-shots is timing out?

"Well" is a word you'll need to use often when hacking kluges like this.

It's just like this:

"Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it.

Brian W. Kernighan"

Except that demonstrating that nontrivial async logic is safe is a thousand times harder than designing it.

John

How so? It has no longterm memory of previous events, so it should work at arbitrarily low rates.

Are you feeding it slow edges?

John

Groan...:P Is this SED or alt.binaries.writingforperfection??

Although, I don't mind the feedback to prevent writing errors in the future..but my writing bugs are the least of my technical problems.

2nd priority...dotting i's (oh fk...apostrophe used correctly?)

D from BC

I have Larkin's circuit in LTSpice.. It's actually tough to beat for prop delay and parts count. The Xor part is cool.. Maybe call it an edge rectifier..I've never seen that before. (Does that part have a name?)

I tend to agree with Larkin... Relative to his cct., everything else is a timing hairball.

However, the Larkin cct changes behavior at lower frequencies.. But..but..but I can still try it in my app which already has a built in 100khz f limiter.

D from BC

When using fast edges but lower frequency...I think I spotted an inversion effect.. In other words...the cct only goes in phase after a certain frequency and 180 out of phase below a certain f.

I could be mistaken and might need a vacation... When I get back I'll try to confirm.

Here's the test circuit I just started to work on. It's rough.. Output is Qnot.

RC values do provide correct operation for 100khz and up. (Note: RC values used are only for evaluation..not actual build values) But.. I've lower f to 10Khz. Note: ( My app never goes below 100khz anyway's...So this is just some curiosity.)

Version 4 SHEET 1 880 680 WIRE 64 48 0 48 WIRE 352 48 64 48 WIRE 64 64 64 48 WIRE 352 96 288 96 WIRE 560 96 528 96 WIRE 64 128 64 112 WIRE -80 224 -80 48 WIRE 80 224 -80 224 WIRE 288 224 288 96 WIRE 288 224 144 224 WIRE 80 272 16 272 WIRE -80 288 -80 224 WIRE -80 288 -240 288 WIRE -48 288 -80 288 WIRE -304 304 -544 304 WIRE -544 416 -544 384 WIRE -544 544 -544 496 FLAG 432 144 0 FLAG 432 0 0 FLAG 64 128 0 FLAG -544 544 0 FLAG 560 176 0 SYMBOL Digital\\\\xor 128 176 R0 SYMATTR InstName A1 SYMATTR SpiceLine Vhigh=5V Vlow=0V SYMBOL Digital\\\\buf -48 224 R0 WINDOW 39 -125 114 Left 0 SYMATTR SpiceLine Vhigh=5V Vlow=0v Td=0.2uS SYMATTR InstName A2 SYMBOL Digital\\\\dflop 432 0 R0 SYMATTR InstName A3 SYMATTR SpiceLine Vhigh=5V Vlow=0V SYMBOL res 16 32 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL cap 48 64 R0 SYMATTR InstName C1 SYMATTR Value 10pF SYMBOL voltage -544 400 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(2.5V 0.1 50000000 0 0 0) SYMBOL voltage -544 288 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value SINE(0 2.5 10000 0 0 0) SYMBOL Digital\\\\buf -304 240 R0 SYMATTR InstName A4 SYMATTR SpiceLine Vhigh=5V Vlow=0v Trise=1nS Tfall=1nS SYMBOL res 544 80 R0 SYMATTR InstName R4 SYMATTR Value 10k TEXT -144 520 Left 0 !.tran 0 300uS 0 1nS

D from BC

It's not that. It's to clean up the output of a comparator in my app. The comparator is getting a damped ring signal due to some unavoidable inductor resonance. I've maxed out the amount of hysteresis I can put on the comparator. All this is in a main feedback loop and the debounce cct has to be low delay to enable the highest system frequency. The higher the frequency in my app... the better. (Well..EMI aside..)

I really believe I'm not doing a bandaid solution..it's essential.

D from BC

The delay in the rc must exceed the bounce time. The rc tau is pretty much the only way this circuit knows what time means.

John

If a $1.50 Coolrunner does the job, what difference does it make that you're wasting 95% of the on-chip resources? We do FPGA designs that run 15% macrocell use, and the customers pay the invoices just the same.

John

The problem, as stated, requires a circuit to operate in four different phases: Phase A: wait for a rising edge, go high when it does Phase B: stay high, ignore edges for 'a while' Phase C: wait for a falling edge, go low when it does Phase D: stay low, ignore edges for 'a while'

So, something with two monostables or latches or whatever is required, because the four states require two bits of state information. And there are two time periods of some (presumably known) duration to be part of the mix. It's required BY THE PROBLEM to have some kind of one-shot to handle that timing, unless you can use higher- speed synchronous logic somehow. And the sensitivity to glitches inside the phases A and D is also required, because you can't determine (at speed) anything suspicious about transitions during those phases.

Asynchronous logic can be scary, but this situation really calls for it.

I posted a simple, fast circuit that works, is hazard-free, and has few of the things that you say are "required by the problem." Remember, the signal has states of its own, so the circuit doesn't have to include all the states you enumerate.

That's no reason to design hairballs.

John

Le Sun, 04 Nov 2007 08:17:33 -0800, JosephKK a écrit:

When I was a kid I did program 6800/6809 in hexa (no assembler available). Well one of my first tasks was writing a line editor and an assembler, all that in hexa.

I certainly would not do that for CPLDs.

Le Sun, 04 Nov 2007 10:44:20 -0800, D from BC a écrit:

Oh, I thought you wanted some debouncing. You don't want debouncing. You want damping. Damping "inductor resonance" is the same as properly terminating a TL. It'll cost you one resistance and maybe an additional cap. Nothing more. And damping the resonant circuit will give you the fastest clean response.

Yes, why make it simple when you can make it difficult.

You're wasting everyone's time with your partial description of the circuit and signal source. All those FF and OS circuits are unnecessary. At the least , it is a simple matter to employ ac positive feedback to the comparator to coast the output through a 100ns ring down time, and then only if for some reason the "inductor resonance" itself cannot be over damped using any one of the numerous techniques to do so. Is this "resonance" due to a length of uncontrolled impedance *wire* running from the nebulous 'power section' to your add-on board? If so, a simple series small resistor goes a long way towards damping a high frequency resonance ( ~100MHz in your case ) while preserving more than sufficient BW for the processing. SHEESH!