Debouncing....at About 1Mhz

Well, there's 4 prop delays from the falling edge input to the output.

And not to be *too* critical, but this is a classic hazard-filled spaghetti-code glitch-driven asynchronous mess. For example, a fast glitch can fire both flipflops. And the circuit has four internal states, one of which is a hangup state, with both flops set; it will probably manage to find its way into that situation, and can never get out.

My circuit is better because it has no unnecessary states, and because it's simple and easy to understand. Much faster, too. The lowpass+schmitt is even better if you can tolerate the delay.

Asynchronous circuits are inherently hazardous, and desperately *want* to screw up, so should be kept as simple as possible.

John

Here's what I've finally coughed up... :O *

Notes

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• Circuit not reduced yet...

• RC values, gate prop, generators will all be adjusted later for proper timing.

• I chose this timing just to use the default gate parameter settings..(laziness).

• 1st time doing so much digital in LTSpice... (Most of my digital is done in CM2000)

Circuit Description

------------------- D latch A2 latches on 1st positive edge D latch A1 latches on 1st negative edge

Each latch triggers a one-shot circuit which resets the neighboring latch. Each one shot period is just slightly longer than the bounce period.

It looks like it works...

Open to comments or feedback...

D from BC

No, it needs to be simpler.

I know guys who would say "gee, I can add a hang-state detector that senses when both flipflops are set for some time interval, then resets both of them."

John

I've noticed the IE seems to butcher this image at my end...I suspect image resize distortion. When I view the file using windows picture viewer, the image looks fine. Viewing might be better on a webpage

D from BC

Brutal! :)

Yup... I now see that 4 prop delay from the falling edge input to the output. Darn..

My spaghetti needs a bandaid. :)

D from BC

So, use a nonretriggerable monostable with rising clock to make a pulse at A, another with falling clock to make a pulse at B, and Set/Reset a flop flop with those. Use the monostable A output to gate (inhibit) the B trigger, and the B output to gate the A trigger. As long as the monostable time is set longer than the jitter window, you're golden. Well, the trigger/output propogation delay has to be shorter than the delay to first false transition...

For retriggerable monostables, the extra edges will stretch the output pulse; if the stable time is guaranteed longer than the monostable period, that's OK too.

The nonclassic solution is filtering followed by a Schmitt trigger. That introduces phase delay, of course, and senses some average over time rather than the initial edges.

Actually.. I've been neglecting to watch out for a freeze up problem.

I had another bandaid in mind..

The bandaid was adding 2 NAND gates and a SR to my cct on

I think I just reinvented John Fields circuit (The circuit with the 2 one shots.)

Ok.....I'm going to look at your circuit. As on..

D from BC

Hairball.

John

That makes it even more complex, and adds new hazards.

It's extremely difficult, or more likely impossible, to prove that a mess like this is safe. That's why asynchronous logic is seldom used where it really matters.

A synchronous state machine can be proven to be correct. And it can have hang states that are not a hazard because it can be proved that they can never be entered. An async machine like this one will be teased billions of times in its lifetime, and if it has a chance of hanging, it probably will.

You'll never prove that it's safe. It way too complex, and way to slow, anyhow.

As has been pointed out a few times, it inverts. So take the output from Qbar.

I'd still go for the lowpass-schmitt.

John

ok ...ok.. I guess it's (correct use of apostrophe) not cool to back off on a spec after some time.. I should have included in the 1st post some dream specs, some lower and upper specs. I do have a real justified technical reason for needing minimal edge to edge delay. Not just for sport... And I do plan on building a debounce circuit this month.

I was trying to make this point.... If the circuit problem is too heavy then I'll settle for simpler longer prop. time designs. Those would be quicker to post and describe. Also, those designs can be an inspiration to faster designs.

Yup... I've done some DTL circuits to reduce chips.

About your circuit.....

Holy frick batman! :O What amount should I put on the check? :)

You did the generator too!

I cheated on that ... :P

Huh...I didn't know the unused pins could be left open in LTSpice...I guess I should read the whole manual someday...It was driving me nuts to hook up all the unused inputs.

Heyy! This is a fun problem :) I've got papers all over the floor from trying to figure this out on my own..

k...I'm gonna take this circuit for a test drive... :)

Thanks. :)

More later... D from BC

You can never prove that a thing like that works right. Which means that it probably doesn't.

Hairball.

John

It seems to be the trend. I realized some of those monostable requirements when I tried to solve the circuit. Also, I suspect John Fields ascii circuit and posted LTspice file use similar approaches. One channel for the positive edge processing. A timing action. One channel for the negative edge processing. A timing action. Some cross resetting and final decoding..

The sequence is something like this.

Trigger on positive edge. Let fuzz pass by. Clear negative edge in preparation for 1st incoming negative edge. Trigger on negative edge. Let fuzz pass by. Clear positive edge in preparation for incoming positive edge.

The pita part is attempting low prop delay for 1st pos edge and 1st neg edge. The SN74LV123A retrig MM has a tpd of 11nS@5V at the top of the datasheet. D from BC

Oh come on... I think JFs (apostrophe used correctly?) has a logical progression with low propagation in mind.

If I understand it correctly..

It's got edge extraction. It's got 2 parallel paths per edge type. And 2 timers to knock out the fuzz.

I'm guessing the required shopping list for this type of circuit is :

A means to detect the 1st positive edge. A means to detect the 1st negative edge. An ignore timer for the fuzz after the 1st positive edge. An ignore timer for the fuzz after the 1st negative edge.

D from BC

I'm checking out how the Deglitch cct behaves when the frequency is varied..

(I forgot to mention in my first post that the frequency can vary but not the bounce period.)

The hairball circuits can react to varying pulse widths and have a large operational BW.

D from BC

It would be simpler to learn how to terminate your signals properly...