It should be a roughly 10 ns positive pulse at every transition of the input. The first such glitch clocks the r-c filtered data into the dflop. Any additional glitches do the same thing. There's not even a metastability hazard. This circuit is simple enough that a humanly-possible analysis can demonstrate, with high confidence, that it's safe.
You don't like it for personal reasons. That's a bad basis for engineering.
John
-- On the contrary, I\'ve used a similar circuit for years as a clean transition detector: .IN>---+----------A . | EXOR Y-->OUT . +--[R]-+---B . | . [C] . | . GND The only thing I think that\'s wrong with your circuit is that at the speed it\'s supposed to be used I think the EXOR chain is going to generate a lot of hash as it follows the bouncing input.
I think I tried that. The R in the dampening cct gets fkn hot! It's not a low energy situation. The ring is from a few unavoidable parasitics..
However, this is uncharted waters for me.. I'll check for goofs..
I really don't believe there's anything I can do in the way of preventive measures. It'll bounce.
D from BC
JL, I'm tempted to replace that RC section with a D ff...
The D ff will hold the previous settled state. It can be clocked by a delay triggered by each edge.
That way.. the circuit works from 1Mhz all the way down to 1Hz and less.
Ok..if I hairballize your circuit a bit :) D from BC
[snip]
I've been thinking all those lines also. I had a "perfect" ratty-edge remover around here somewhere... now I can't find it :-(
Yep.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
America: Land of the Free, Because of the Brave
Le Mon, 05 Nov 2007 08:29:55 -0800, D from BC a écrit:
Why is it getting hot? What are the voltage and parasitics estimated values? What is the source?
If the average DC is high enough and the L/C impedance low enough so as to pose pb, then use an AC termination (series RC, where C is a feew times your C parasitics). Depending on the configuration you can also use source series termination.
Google about TL termination.
-- Thanks, Fred.
It's possible.. but I don't think so..
It's part of an smps controller.
I'll post the source of this problem as another topic.. It involves parasitics (inductance and capacitance), hysteresis limitations, current sensing and control loops.
I posted what I thought was an interesting and challenging problem. It also looked like a classic problem..so I thought there might be an already known solution.
The debounce problem was simple to describe... but surprisingly tricky for me to solve .
D from BC
Last time I studied key-debounce was for my old TRS-80 back in 1980, and they had a nice little solution.
Maybe this might work, I'll use 1 OR gate.
A ------------ OR ---------------- O/P B--- | |-- -------C-----| R gnd
Start with everything at 0.
Input A get's a "1", the O/P goes Hi to "1" and feeds to "B", doesn't matter now that "A" is bouncing about, the O/P stays Hi for the RC time, by the O/P feeding "B" via "cap C". (R can be the gate input resistance).
The gate resets when the RC times out ready for the next "1" delivered to "A". Regards Ken S. Tucker
I don't know what you mean by "hash." If you mean emi, well, any gate that follows any signal generates "hash." Your circuits have lots of logic transitions, too. That's what logic is for, to process signals.
So you're saying that this signal is so bad it shouldn't be allowed to go through gates.
John
Hey, Jim, how's the bod?
John
That will break it of course, but that's your option.
It does already.
Sure. It's not my job on the line.
John
Walking, mild pain, cleaning up the bed rash from 72+ hours lying on my back :-(
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
America: Land of the Free, Because of the Brave
-- Not a lot, just what\'s required to set in motion the chain of events which accepts the first edge and suppresses the rest. Your circuit sits there generating very high-speed, probably high-current edges every time the input signal changes state.
Now, I haven't done a full analysis on this circuit, but the biggest drawback on being this edge triggered is the vulnerability of a noise spike, esp. on that positive edge, giving a false trigger. That was why I always appreciated those Moto debounce chips (for slower stuff) as it debounced both edges equally. You just had to live with the delays...
Charlie
That's what this circuit was supposed to do.
"Probably high current?" Logic does tend to use power when it switches, I suppose.
Yup, sounds like.
Oh please. You can say that about any digital logic.
Joh
Yeah, thinking about this, the problem definition becomes, instead of a four state machine, a two state machine:
Detect tranistion, change output state WAIT
Simple, and I am sure, full of gotchas, especially in that WAIT state... ;-)
Charlie
It's problematic to say that any asynchronous machine has states. My circuit has only one flipflop, so I think it has two states: flipflop set, and flipflop clear.
John
The wait state just has to exceed the worst-case undefined input time.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
America: Land of the Free, Because of the Brave
-- Then, unfortunately, since it didn\'t suppress the multiple edges propagating through your EXOR chain, it\'s not working like it should.
-- Yes, but for best noise immunity (if the period of the input signal is known) the wait state will end just prior to the next expected edge.
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