Breadboarded 74HCT7046 PLL very unstable

Yeah, that does work well. A similar approach is to use little (~3/16" or so diameter) circular "punch-outs" (chads) of copper-clad PCB material... you trade off the use of super glue (...careful not to glue your fingers together...) for not needing a Dremel/drill-press setup (...careful not to drill into your fingers...); little baggies of such chads are available commercially.

Somewhere, deep in my past, I had a drill-bit that drilled a lead hole AND scribed a pad... really handy! ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

X-acto knives do a great job on copperclad. Do be careful, though.

With a 7046? You'd need a trimpot to get it close enough to lock, and a little temperature change would probably push it out of lock range.

John

Yeah, all digital with a cheap fixed clock, 50 MHz or so, would be bulletproof.

John

Another scheme I've used...

...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

No, I've torn the original design up and started over. I now have:

- A Hogge phase detector, built from a HCT74 D-flip-flop, a HCT86 XOR and a HCT125 O/C buffer - A HCT04-based TTL oscillator with a BB419 varactor providing the VCO functionality - An R/C loop filter (currently 30k series R, 100pF capacitor to ground; they were sitting on my desk and seem to work)

I need to look at the loop filter -- I suspect I need an opamp buffer for the VCO (the frequency is a little off when the loop is 'locked'), and I'm willing to bet the filter's cutoff frequency (if not its entire design) is completely non-optimal.

--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

A loop with not enough DC gain will leave the _phase_ off by a little. If the _frequency_ is off, the loop is not locked--the phase error is increasing without bound.

You may have a false lock, where the loop fetches up at some frequency offset due to excess phase shift in the loop filter.

You really need to draw a Bode plot of the loop filter--you keep using simple RC lags, which won't work properly. Either their cutoff frequency is beyond the loop bandwidth, in which case you really just have a first-order loop--inevitably a poor performer--or it's inside the loop bandwidth, in which case you have a marginally stable loop. (There's an intermediate situation as well, where your phase margin is declining, but that's not very different from the first-order case.)

An op amp lead-lag filter is the simplest kind you should consider for a clock recovery job, where keeping the eye diagram open requires careful control of the peak phase error.

Cheers

Phil Hobbs

[snip]

Here ya go...

I had to fudge the delays a little bit to get "lock". Probably better with 74AC... or similar.

The original was done with TTL and those DIP-sized LC delay lines for some NRZ bus... I can't remember what now.

Though I have several patents in PLL components, I don't like PLL's for "burst" extraction of data... they tend to be slow, and need a big preamble. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

Use a small capacitor between the varactor and the oscillator to reduce the range, and maximum capacitance. Start at about half the maximum capacitance of the varactor, and go lower if you need to.

--
For the last time:  I am not a mad scientist, I'm just a very ticked off
scientist!!!

Do you need the clock?

If all you want is the data, then you can do it all with digital logic. You need a 10x or 8x clock to drive a FSM. You can work out the details with a bit of playing with pencil and paper.

The current-state is just the number of ticks since the last transition. The other inputs are the current signal and previous signal.

The outputs are the new-data-bit and a data-valid (clock enable...) signal. You might also get out an error signal and/or an end-of-packet.

You can calculate how long a run you can track if you know the accuracy of the transmitter clock and the accuracy of your local clock.

It's easiest to think of implementing it in a big ROM. Then you can figure out how to simplify things to fit in a smaller ROM with a bit of logic.

--
These are my opinions, not necessarily my employer's.  I hate spam.

OK, that's fair enough, but how do I go about selecting suitable component values?

For a basic 2-resistor-1-capacitor lead-lag network (per

page 4), there are two time constants, produced from the component values. Alternatively I can work backwards and use the time constants to come up with component values (by plugging in a value for e.g. C1 and extracting R1 and R1+R2 then working backwards to get R2 from that).

But what do I set the time constants to? How do I know it's working?

I also found a PLL design tool at

design-tool.php, but that asks for: Phase detector gain VCO gain Loop bandwidth Damping factor Divider value Scaling resistor

"Are you sure you know what you're doing?" "Not even close."

Thanks, Phil.

Philip Pemberton wrote: > On Tue, 28 Dec 2010 10:26:01 -0500, Phil Hobbs wrote: >

It's not too bad, really. (I designed my first PLL before ever having seen another one. Right out of university, I was very fortunate to land a job designing high performance PLLs for satcom--me with my brand new astronomy degree and hobby electronics background. I was completely at sea, but recovered fairly fast. You will too.)

Key fact 1: When you put circuit blocks in cascade (the output of one feeding the input of the next), the total gain of the string is the product of the gains of the blocks. (This is after any interactions are included, e.g. the input of one loading down the output of another.)

Key fact 2: The behaviour of a feedback loop is governed by its _loop_gain_ AV_loop, i.e. the gain calculated by starting anywhere in the loop and calculating the cascaded gains until you get back to the same place. The degree of stability of the loop is measured by its

*phase margin*, i.e. how many degrees you have to go before the negative feedback becomes positive and the silly thing oscillates. Phase margin is measured at the unity gain cross, i.e. where |AV_loop| = 1. Relying on phase margin for loop stability is not a foolproof procedure, but it's almost always good enough for op amps and PLLs. (*)

Kphi: The phase detector gain is how many volts (DC) the phase detector puts out for a given phase error in radians, i.e. dV/dPhi measured at the operating point of the loop. For PDs with linear characteristics, it's equal to the supply voltage divided by the phase range. A phase-frequency detector (e.g. PD 2 in the 4046) has a sawtooth characteristic, so Kphi = Vdd/(2*pi). An XOR phase detector's characteristic is a tri wave, so its phase range is only pi radians, and Kphi=Vdd/pi.

With a sinusoidal phase detector such as a diode bridge, you actually have to take the derivative--Kphi = Vpeak/(1 radian) at zero volts output.

Kvco: This is the sensitivity of the VCO in radians per second per volt, i.e.

2*pi*dF/dV. For a 4046, again, it's Kvco = 2*pi*Fmax/Vdd. (You have to distinguish carefully between F, the VCO output frequency, and f, a frequency component of the control signal inside the loop.)

As an aside, note the asymmetry between these two: Kphi is in volts per radian, and Kvco is in radians *per second* per volt. When you multiply them together to get the loop gain, instead of a dimensionless ratio as in a normal feedback amp, you wind up with a loop gain in frequency units!

This is the main thing that confuses people about PLL design: considered in terms of phase, a VCO is a perfect integrator, so the actual gain of the VCO isn't really Kvco but Kvco/(j*2*pi*f). There's a one-pole rolloff built into the PLL's loop transfer function from the start. (Remember that f is not F.)

Since the VCO, phase detector, and loop amplifier (including the filtering components) are all connected in cascade, the loop gain is the product of all of them:

Kvco AV_loop(f) = Kphi * -------- * AV_filter j2pi*f

The loop amp's voltage gain, AV_filter, is

1 AV_filter = -------------- * (1 + j2pi*f*tau_zero) j2pi*f*tau_int

where tau_int is the integrator time constant (input resistor times feedback capacitor) and tau_zero is the zero's time constant (R_zero times feedback capacitor). (R_zero is the resistor in series with the feedback cap.) You can verify this really easily from the formula for the gain of an inverting amplifier.

So you stick this into your favourite math program, and start playing with the time constants till you get a loop with adequate bandwidth, phase margin, and ripple rejection.

My usual way to start playing is to note that if you ignore the zero, the loop gain is Kphi*Kvco AV_two_ints = - ------------------- (4*pi^2)f^2 tau_int

so the unity-gain frequency is

sqrt(Kphi * Kvco /tau_int) f0_two_ints = -------------------------- 2*pi

Adjust tau_int to put this at about BW/1.27, where BW is the loop bandwidth you want. The factor of 1.27 comes from what we're going to do next, which is to put the zero right at f0_two_ints, by setting

tau_int = 1/(2*pi*(BW/1.27)).

The zero contributes a gain of 3 dB and a phase of +45 degrees at that point, so your phase margin is at least 45 degrees. Because the zero shifts the unity-gain cross out a bit, the phase margin is actually about 52 degrees, which makes a nice stable loop with a good tradeoff of bandwidth and overshoot). (You could put the zero a bit lower in frequency to get more phase margin if you like--don't go below 45 degrees.)

You'll probably want to put another cap across R_zero, to get some more ripple sideband rejection, which will require some adjustment of tau_zero to keep the phase margin, but this simple procedure will get you most of the way there.

There are three last things to worry about: (1) getting the loop polarity right,(2) making sure you used the right value for Kphi, and (3) thinking about signal level dependence.

(1) Phase detectors have a periodic characteristic, which means that their V(phi) characteristic has to pass through the operating point twice per cycle. The two crossing points will have opposite slopes, i.e. one will be stable (negative feedback at DC) and one will be unstable (positive feedback at DC). With symmetric phase detectors such as XORs and diode mixers, the loop just chooses the right one automatically. With sawtooth phase detectors, you have to make sure that the stable null is on the slope of the sawtooth and not the near-vertical bit.

(2) For a Costas loop or other more glorified thing, Kphi is usually less than Vdd/pi--there are various ways of looking at this, but figuring out what dV/dPhi is usually isn't too hard. You can easily be off by a factor of two if you don't think about it, which will mess up your loop calculation completely--you have to move the zero down in frequency to compensate, or your phase margin will be way off.

(3) Another thing that'll mess up your calculation is if the input signal level varies. With XOR phase detectors this won't be a problem, but with linear PDs such as diode bridges, Kvco is proportional to the input signal level, so the loop gain drops for low signals. This leads to instability, as above. If your signal level can shift, you have to take account of it in the design by leaving a lot of extra margin.

Cheers

Phil Hobbs

(*) Tim Wescott and others can tell you all about cases where it's emphatically _not_ good enough, but those usually involve motors and heaters and manly stuff like that. Usually nobody dies if a PLL bounces around a bit before it locks.

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

That sounds useful. Where do you get them?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

Good question. I once had one that also drilled a hole in the pad, for thru-hole. I'd love to find another! ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

The bag I have came from a ham fest. I did a little Googling without good results for people selling them pre-packaged; apparently a lot of people do just make their own using a cheap hand punch. See, e.g.,

Do post if you find one...!

---Joel

Jim Thompson Inscribed thus:

Yes, me too ! When you do let me know :-) I used to have a set of three of them, different sizes, heavens knows where they disappeared to...

--
Best Regards:
                     Baron.

Thanks, Joel. That web link and pictures there is wonderful! I'm going to try this out, very soon. I need to see how it goes, but it seems very practical.

Jon

Make your own when needed from pcb blanks. Steel wool/copper clean the board first, then punch out what you need. Avoids tarnish.

That tool - the Neiko hand held power punch - looks very close to the Harbor Freight punch mentioned at the url Joel posted. (I have the HF tool, but it's not in their catalog now.)

Ed