I'm running a Spartan3E (100e, vq100) with the VHDL below.
It's connected to an LED display. The CLOCK_OUT, for some reason, is bouncing before settling. When I connect an audio meter to the line, I can hear it ringing on and off very quickly before settling back to off. This is causing my DATA_OUT to be clocked many more times than once. The VHDL below is a trimmed down version of what will be a more complex project -- I'm just starting simple to assert that everything works.
I have the large divider on it so that I can visually see each byte getting clocked onto the LED panel. The behavior I am seeing is the entire panel filled with each byte (because of the bouncing CLOCK_OUT). The panel should be counting across.
My CLOCK_OUT pin is defined as the following in my UCF file:
NET "CLOCK_OUT" LOC = "P3" ;
I have tried, to no success:
NET "CLOCK_OUT" LOC = "P3" | PULLUP;
Thank you for any help!
entity driver is Port ( CLOCK : in STD_LOGIC; ACTIVE : in STD_LOGIC; CLOCK_IN : in STD_LOGIC; LATCH_IN : in STD_LOGIC; DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0); DATA_CLOCK_OUT : out STD_LOGIC; CLOCK_OUT : out STD_LOGIC; LATCH_OUT : out STD_LOGIC; DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); end driver;
architecture Behavioral of driver is signal mode : STD_LOGIC := '0'; signal divider : STD_LOGIC_VECTOR(23 downto 0) := "000000000000000000000000"; signal output : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; begin process( CLOCK ) begin if( rising_edge( CLOCK ) ) then if divider="000000000000000000000000" then if mode='0' then CLOCK_OUT