74HC74 pulse shaping

The schmitts help if there are slow clock or chip-select edges or ringing, like if the signals travel over a cable or a big board. They don't help with multi-chip serial data chains. Well, they maybe add a little prop delay.

An RC near the destination chip can lowpass filter noise too, if the chip has schmitts.

Ooh, SN7476 JK flop. Had the weird "ones catching" hazard. JKs were once the rage.

More like 500K, as I recall.

Or else design it so that it works.

Tpd out helps the skew situation, until the clock rate gets extreme.

Den torsdag den 25. august 2016 kl. 21.16.03 UTC+2 skrev John Larkin:

without that spec you have to hope they designed it to work or add hacks

you have to guarantee that Tpd is bigger than Thold for a cascade

with zero hold it is easy, just route the clock in the opposite direction of the data flow

-Lasse

I think John doesn't understand tpd at all. If you have a 10 ns input hold time requirement and the output driving that input has tpd less than 10 ns it gets complicated to design a circuit that works without adding goofy things like delay lines.

In this case it would be hard to imagine TI not designing the chip with a tpd less than 10 ns or they'd see problems from lots of customers. I wonder why they don't spec this parameter. I guess they figure you won't be mixing their part with any other parts in the same chain.

Unless tpd is negative... lol

we can probably assume that it isn't without it being in the datasheet ;)

-Lasse

I've never used the original 74xx series for anything, afaicr.

A little matter of 35 years ago, in my first engineering job doing satellite telecom, I used to use a lot of 74S112 JK flops because they were a fair bit faster than 74S74s.

Cheers

Phil Hobbs

I am pretty sure anyone with a device with a negative tpd won't be putting that info in a data sheet and selling it... I know I wouldn't.

Or maybe that is not right. If the negative tpd magnitude is still less than the setup time... you can't do anything quite as useful as I would want. :(

Thanks, Rickman, for the long answer, it does provide some needed clarity.

We oughtn't 'assume this does not happen'; here's the datasheet

One can note that the clock input (CLK) of an 'HC74 is buffered and inverted, to make /BCLK, and then to make BCLK; those two signals operate transmission gates (analog switches). The conductance of those switches is dependent on a PMOS transistor when transmitting a HIGH signal, and on NMOS when transmitting a LOW signal. Whichever transistor is attached to /BCLK will get a more marginal drive than that on BCLK. So, we must expect the thresholds to depend on initial state of Q, /Q, and D . Ideally, we'd check with (D, Q) = (0,0), (0,1), (1,1), (1, 0)

With transmission gates, thresholds DO depend on the channel voltages ("outputs").

Good; this means that we test with a signal that barely clocks the FF, then (in order to make the next observation) we keep the clock voltage steady for the minimum clock width plus the propogation delay so as to record an output, while changing the D input and waiting for some setup time before a second clock event, then make a dip in the clock voltage that lasts a second minimum clock width, and drive the clock HIGH. D can start changing before propogation delay is over.

There's approximately 500 ns available for all this, because the data sheet insists all clock transition be complete after that. The datasheet values for 4.5V mean you have to deliver D and CLK signals accurately over a minimum time of

John Larkin has suggested 'just test it'; I don't have an arb that can do this in the 139ns time with 1ns resolution, nor in 500 ns time (presumably, about

If one DID test this way, note that the (D, Q) states of (0,0) and (1,1) would still be undetermined, because those don't change the output regardless of whether the clock is active or no. You can make a different test, using SET and RESET inputs, but the timing margins are a new puzzle.

An earlier posting claimed hysteresis on clock input. I'm dubious that it was actually observed.

I bet you kids never used RTL or DTL, either.

I did a nice successive-approximation ADC with discrete transistors.

Hmmm... there is a reason why things like this are verified by measurements rather than purely by analysis. You say the N-MOS transistor has more drive than the P-MOS transistor, but given the high impedance of the gate being driven that does not equate to a lesser voltage drive.

I don't follow the need to analyze this anyway. The original discussion was about whether hysteresis is useful on a clock input and whether it can even be detected.

I'm not clear at this point what you are trying to measure. The data sheet values show you how to use the device properly. Noise on the clock line is not "proper" operation and is very likely to violate a number of the specs.

You do bring up a point. If the FF is double clocked by noise during the rising edge, will it make a difference? It would only make a difference if the D input changes between the two clock events. This would be a *very* narrow time window. It's hard to imagine any outputs would change fast enough to give a different result. The only impact would be on the data input hold time which would no longer be 0 ns in this case, but now the time between the two clock events. This could only cause an error if some other device on the same clock were feeding this data input and had a much faster tpd... *much* faster. If your FF has a more significant hold time requirement this gets to be a more significant issue.

That's possible. It seems odd anyone would add hysteresis to a chip input without mentioning it in the data sheet. That alone makes me suspicious.

Well, '74LS...' is DTL. ;-)

Why?

I designed a level translator with a negative Tpd and it showed as negative in the datasheet. Standards demanded that delay be measured from 50% to 50%. The threshold wasn't in the middle so... I argued the case for measuring from the source to destination logic thresholds or from actual threshold to output but lost.

Hey, guys, it's really comforting to have a response on a thread that was m ore than a year old when I camped on. Good going, seems like a good group and a knowledgeable bunch.

And, yes, the NXP (only!) datasheet refers to a Schmitt on the clock input of the HC74. Here's a link to the sheet: nxp.com/documents/data_sheet/74HC_HCT74.pdf ...and if you look at the top of Page 1 they actually say that it's Schmitt ed on the clock input, and on Page 2 the functional schematic for the part shows a Schmitt on the CP input. Other datasheets, like the TI, have a min imum risetime specification, but I don't see that here for the clock input. This was my beef in the first place, a seemingly-standardized part that d iffered from others with the same number.

My application was a frequency synthesizer with a 60kHz loop frequency. I used one of those tiny cylindrical crystals, like you see in watches, but c ould make it oscillate reliably only using a 2-transistor discrete Franklin oscillator circuit, and even then it goes through some gyrations starting up. The output of this reference was a bit sluggish, which was no problem for the NXP part, but other '74s did not want to trigger with risetime in t he 200ns range.

Since going through all this I have learned the error of my ways, however, and am now using a 6MHz crystal, with the classic inverter type of oscillat or and an HC390 to bring it down to 60kHz. The drift-with-temperature of t he watch-type crystal was being multiplied up to the synthesizer output fre quency (about 10MHz), which was totally unacceptable. The 6MHz rock is qui te stable. A pox on those tiny crystals!

There are ways to temperature compensate watch type crystals which helps stability a lot.

Watch crystals resonate in a tuning-fork mode, which involves a lot of mass motion and frictional damping. Also, frequency-multiplication increases ph ase noise amplitude by the same factor. Long ago, working on the first ci vilian direct broadcast satellite system, I did a 110-115 MHz synthesizer t hat was multiplied by 120x to form the LO of a 12/14 GHz link. That 120x ma de the phase noise 42 dB worse, which was fairly heartbreaking at the time, though it eventually worked fine.

Cheers

Phil Hobbs

I've never had much success using Schmitt gates as crystal oscillators.

I mostly buy entire XOs. They are small and cheap, usually come tuned to a couple PPM, and always oscillate.