74HC74 pulse shaping

Uh, I think that is three PER mission. How many times would we have needed to send people before a crew returned?

I'm guessing there would've been only one shot at it, success or not. If we had a total loss of crew on the first mission it's likely there wouldn't have been any followup, at least for a while if ever.

The alignment of the planets was only right for a minimum-energy trajectory IIRC circa 1974-1975, and wouldn't have been favorable again for quite a while. At least long enough for a new administration and all that comes with that.

Can use it as an R-S. Input to /CLR, inverted input to /PRE, CLK and D = GND. You'll need one transistor to perform the inversion if you don't have the complement handy (or you can use a transformer if it's AC, or a hybrid if it's narrowband).

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

The Boss Octave Divider does something like that I think:

You want to use it in set/reset mode, with possibly some positive feedback. Clock input MUST be a fast edge to operate properly. So, connect D and CLK inputs to any convenient logic level, to inactivate those. Apply your input to /Preset, and its inverse to /Clear. A biased transistor can be an inverter for this purpose, if the complement isn't otherwise available.

To prevent multiple-transition events, a resistor, or R-C in series, from Q to /Preset, and from /Q to /Clear, might be beneficial.

If this is a part of a clocked design, you could apply the slow signal to D, and clock the flip/flop with a system clock signal, but of course that only generates system-clock-synchronous edges, which might be unwanted.

Simpler than that... tie the Clock, Data and Set inputs low. This makes the quiescent state a high on Q and a low on Qnot. The input is connected to the Reset input. The Qnot output will be the inverse of the Reset input. Since the Q output doesn't change there is no way to get hysteresis from this circuit without another active part.

Okay then, you need to make it clear that /CLR is pulled up to VDD in the quiescent state.

Ckt is a waste of time since OP's problem is being caused by overloading of his signal source. It's much easier to fix that.

Given the definition of "canonical", there isn't one!

Yeah, that gets you a NOT or BUF if you need one. Probably with enough logic inbetween that it acts like a schmitt trigger. Wonder if you could put positive feedback around it to bring it back.

Actually, when you're using the "unstable" (both async inputs active) state, you don't get buffer, only two inverts, isn't it... nevermind.

Tim

It wouldn't work at all if that weren't the case. You just didn't think about it very hard.

I agree that it's a waste of time, but not for that reason. Overloading won't usually cause pseudo-differentiation like that--it's probably a too-small bypass cap plus too-high supply resistance someplace.

Cheers

Phil Hobbs

Thanks for the tips. I think I have an idea - I'll get back to you!

Someone along the way sort of verbalized this...

Ignore the D2A and A2D elements... replace with wires... just my gimmicks to separate digital-realm simulation elements from the analog-realm allowing both digital (bits) and analog (voltages) to be seen (and speeds up complex mixed-signal simulations. ...Jim Thompson

It most certainly would if not for the setup violation, you lift the CLR until the voltage level decays to CLR threshold, then the FF resets.

It does too if the signal source is ac-coupled into the circuit expecting 100kR loading. The coupling is a high pass and when you overload you move the breakpoint up in frequency attenuating the lower frequency components of the square wave.

He means this one: "In mathematics and computer science, a canonical, normal, or standard form of a mathematical object is a standard way of presenting that object as a mathematical expression. The distinction between "canonical" and "normal" forms varies by subfield."

That makes no sense. A flopflop is not a mathematical object.

Flopflop? LOL.

He means a prototypical FF squarer...

In other words, it would work except that it doesn't. The OP wanted to clean up the input waveform, not to make a narrowish pulse synchronized with its leading edge.

'Fred', just for once, why not do like the rest of us, and say "Oh, right, I get it" rather than ginning up some outrage to try to cover up a mistake that most of us wouldn't care about. I make much worse mistakes than that all the time, some of them displayed on SED. No biggie. You can blame it on my lack of clarity if you like. Since nobody is actually going to do this, it doesn't matter.

Well, I suppose thatt's possible if it's audio gear. Lots of strange things are done there, I expect. But in a normal logic system, you'd never ever do something of that sort. (Which is why I agreed with you about the general uselessness of the kinds of kluges we're discussing here.)

Cheers

Phil Hobbs

The configuration I described is the standard FF one-shot, so naturally it' s what registered with your description. You only need 5ns set-up to make i t work, so give it 10, that's a real small RC in series with CLK. Your circ uit fails if the input pulse decays to 0 during the positive half-cycle btw .

e.)

But we were discussing the circuit I described, not the one you misunderstood. And no, it doesn't fail that way. The !clr input stays high in that instance, unless the input waveform decays to 0 faster than the time constant of the AC coupling network, and has enough drive to pull the !clr input all the way to the logic threshold. Given the OP's description, that's a real genuine reach.

As I say, nobody's actually going to build this, so it isn't important. Putting RCs and stuff on logic parts is a good way to get a lot of midnight phone calls. It was just an interesting exercise, like the guy who made a working AM radio out of 555 timers.

Cheers

Phil Hobbs