IRL I don't think there's anything this configuration of the 'HC74 could do but oscillate; with an RC network from not-Q to not-CLR and D, CLK, and not-PRE grounded.
But with these models from the Yahoo LTSpice users group the LTSPice time domain looks like it manages to find some other metastable state and sits there spinning its wheels.
Can anyone suggest some ICs that could bust it out and get it to square-wave in the sim? Thanks
plz use this link instead
74HC132 or if you just want simplest then 74HC14
Are we supposed to know what the two traces are in the circuit?
If they are the two ends of the resistor, there is something wrong. I expect it is the model of the FF. Perhaps the model is not gate accurate. Try driving the CLR- input from a square wave and see if the Q- is inverted from that.
-- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
The voltage gain from \Q to \CLR is low, and there's no schmitt action, so you can get a stable negative feedback loop. It would likely oscillate at a higher frequency, where the logic prop delay becomes important.
Why not use a schmitt inverter? This circuit could be rescued, but it would take more parts.
Maybe "ground" C1 to Q?
But I wouldn't trust the Spice models for what is basically analog behavior.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I noticed just now I made a mistake setting up the sim, when using these digital models one is supposed to set the line:
SpiceModel: VCC 0
at 0
not VCC 5
as I had it.
and VCC=5 SPEED=1.0 TRIPDT=1e-9
for SpiceLine.
Not super intuitive but is what it is I guess I don't use the digital models often.
No guarantee it will fix this particular situation but it should make the models actually, like, work in general
Check this out someone actually got a patent for this back in 1990 (the crystal probably helps a lot):
I noticed just now I made a mistake setting up the sim, when using these digital models one is supposed to set the line:
SpiceModel: VCC 0
at 0
not VCC 5
as I had it.
and VCC=5 SPEED=1.0 TRIPDT=1e-9
for SpiceLine.
Not super intuitive but is what it is I guess I don't use the digital models often.
No guarantee it will fix this particular situation but it should make the models actually, like, work in general
Actually meant \CLR to \Q, the gain inside the IC.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
The easy thing to do to get a square wave is the schmitt inverter, I'd like a low frequency (10s of Hz) with the Q and not Q outputs but I don't wanna use a large R, large cap, wanna use a small R and cap that's relatively cheap to get tight tolerance/tempco on the components.
The easy thing to then do is run a higher frequency from the standard schmitt inverter with smaller Rc, C into a divider chain.
But it would be cool if there were some self-oscillating structure of flops that did it all without needing the Schmitt inverter at all, so far my attempts to find it have been unproductive though
If you have Q and not Q whether from a flip-flop or just from a set of appropriately-connected inverters it might be possible to bootstrap the RC constant capacitor somehow instead of grounding it.
Way back when I did get CMOS 4013A to oscillate sucessfully. I seem to remember it needed 2 caps and 2 Rs though. Was fine until the buffered series 4013B took hold and 4013A became hard to get. The extra internal buffer stages refused to play such dirty tricks.
piglet
Your circuit is simply wrong: there is a stable state with both Q- and CLR- high.
The classic oscillator (though bad) is to use a Schmitt with integrating feedback.
-- -TV
An idea can be patented even if it does not work.
-- -TV
I think not. The PRE- pin is grounded. If CLR- is high the Q is 1 and Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logicall y wrong with the simulation... which is very possible if the FF doesn't ini tialize properly.
-- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
For some people, getting patents is a kind of addiction.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
With the error that I made wrt setting parameters corrected and the sim tested such that the flip flop divides down and otherwise operates correctly here is the output in the former configuration, with more clear labeling of voltages. also no oscillation.
I think the oscillator relies on the 0/0 state at the not-PRE/not-CLR inputs being metastable to start up, but the model's state is not actually metastable.
e
Q- is 0. The circuit should work in simulation. If the waveform shown in the picture is anything relative to the Q- output, there is something logi cally wrong with the simulation... which is very possible if the FF doesn't initialize properly.
Metastability is not needed. Gates in the FF drive the corresponding outpu t high when each input is low. So both Q and Q- will be high when the CLR- input is low. There may be something going on internally if you were cloc king it, but clock is grounded.
This circuit is just an inverter between the CLR- and Q- signals.
When RC went low, the Q- output should have gone high. Not sure what is st ill wrong, but again, I suggest you connect a square wave to the CLR- pin t o test the operation of the FF. Q should stay high while Q- is the square wave inverted.
What is going on with the initialization statement? I don't see a "res" si gnal.
-- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
But \preset is grounded.
It's an off-label use, but most flops will act as a net inverter in that circuit. Spice may well not model that mode correctly. But the voltage gain is typically low so the whole thing might stabilize near Vcc/2.
More phase shift around the loop can make it oscillate. A gated, edge-triggered one-shot is sometimes handy, so I've used a similar circuit to make a flop clear itself, but with a higher-order delay than the single RC. An RLC works, or a PCB trace delay line. A dual delay, RCRC, might work too.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
You might try a real flop. The model may not properly handle this case.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Doesn't pass any signal at all when I do that.
I removed some other stuff before posting but forgot that, sorry
I found a thread on the Yahoo LTSpice users group that might be relevant,
"Hello!
I think I found an error in the model 74HC74 in 74HC_v.lib.
When I ground D, CLK, PRE und CLR then Q is 0V and /Q is VCC but both Q and /Q should be VCC
see function table page 4
Please can someone verify this error and maybe someone can correct the LIB.
I'm not qualified to correct it.
Thanks for your help!!!!!
Best Regards
Harald"
Looks like a corrected model may have been posted in the thread but it doesn't look like the model file I downloaded has been updated, nothing in there about the 'HC74 being revised after the date of the above thread (2017)
"* 74hc.lib
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