74HC74 pulse shaping

If there truly is hysteresis there (I doubt it), apply a DC level that you slowly raise until the output changes state.

There _is_ regeneration in the internal R-S flops, but I doubt that it will affect the clock input.

ALL the datasheets I've seen spec a maximum risetime at the clock input.

On the other hand it _is_ possible to make such a flop... it's just _not_ in a 74HC74. ...Jim Thompson

Yeah I was going to say that a Schmitt would guarantee clock skew and it would be different for every part on the board.

Eh? It's absolutely bog standard 4000 as far as I can tell:

Tim

Just connect q-bar to D to make a divide-by-2. Tease the function gen into clk to see the clock voltage range over which it divides properly.

Or apply a slow triangle, from 0 to Vcc, to clk and and scope the clock and Q. Observe the clock voltage levels as the output transitions.

Every part can have different clock thresholds, schmitt or not. For most any modern logic, PCB trace routing can easily be in the neighborhood of flop prop delay, so a shift register or a state machine can potentially malfunction because of slow risetime or clock trace routing. Avoiding ringing is yet more fun.

We use EclipsPlus flops, with 350 ps typ prop delay, which isn't much PCB trace. Some of our stuff uses the NB7V52 flop, with 200 ps prop delay and 35 ps edges. That one is really tricky.

You make it sound very complex. You don't need to "infer" anything. When the AC portion of the signal is large enough it will clock the chip. When it is too small it won't. Find the high going threshold by adjusting the DC level without any AC. Then add AC until the circuit triggers on each cycle. The minimum of the combined voltage is the low going threshold. Nothing to "infer" just observe the FF being clocked.

How would a Schmitt add clock skew? Are you suggesting each part will have different threshold voltages? Isn't that true for logic without a Schmitt clock input?

If the clock edges are slow enough that Schmitts make a difference on one c hip, they're probably slow enough to make skew a worry.

Cheers

Phil Hobbs

I assume you are speaking from a lack of experience with digital designs. Any board can have signal integrity issues. Any clock can have a very minute amount of non-monotonicity on the edges. The threshold of a standard logic input operates over a very narrow range. It takes only a very small amount of noise on the rising edge of a clock to double trigger sequential logic. That is why signal integrity is an important issue in digital designs. I don't see how a Schmitt input on the clock could possibly cause a problem. You don't need slow edges to find utility in a Schmitt trigger input.

find utility in a Schmitt trigger input.

What use is it if you have nice crisp edges? It won't hurt, but it won't help either.

Cheers

Phil Hobbs

find utility in a Schmitt trigger input.

What use is it if you have nice crisp edges? It won't hurt, but it won't help either.

Cheers

Phil Hobbs

I don't know what you mean by "crisp". A fast edge is less vulnerable to noise creating problems, but not immune. I think you feel a fast edge just doesn't have problems with noise. If they are fast enough, perhaps the logic filters any noise because it has to be a very fast noise pulse. But I don't know what you mean by "crisp".

Any clock can be corrupted by a small amount of noise. Logic inputs are very susceptible to noise at the threshold crossing.

In order to detect clocking, you will want to connect 'D' to '/Q', so each clock event causes an observable change (output toggles). There may be two distinct thresholds, one for Q initially high and the other for Q initially low. After determining those two minimum clock levels for HIGH, do you then bump up the peak values and adjust the trough until clocking no longer occurs? That gives you two maximum clock levels for LOW.

What if, in a range of nonclocking behavior, the flip/flop oscillates? Would that mean the clock doesn't have hysteresis?

What if the four values indicate hysteresis when Q is high, but not when Q is low?

No, a fast-slewing clock has noise immunity because only a high amplitude high frequency noise component can add to a large dV/dt signal to cause false clocking. Logic outputs in a system undergo settling after each clock pulse, so each data signal has stopped ringing and only noise that exceeds the logic margin could invalidate the data during the next clock pulse.

Clock signals, and the data they clock, are insensitive to noise. The purpose of the clock, is to deal always with logic inputs that are NOT near their threshold crossing.

I think you are making this more complex than it is. If you measure a clock input as having hysteresis only when the output is in one state and not the other, I'd be happy to discuss that with you, until then I will assume this does not happen in real logic.

Hysteresis means there will be a different threshold for a high going transition than for a low going transition. On a rising edge clock input, only the rising edge will produce an effect in the device. So you will not be able to directly observe anything other than the rising edge.

However, if there is hysteresis, a non-monotonic rising edge that crosses the rising threshold twice will not have an effect on the second transition unless it also crosses the falling edge threshold and so be indirectly observable. Let me draw some pictures...

.----------- / / Vth -----------/\/------ / / / / /

---------'

,, Output / \

---------------' '------------

Non-monotonic edge - No Hysteresis - two detectable transitions of Vth(H)

Clearly with no hysteresis every transition of Vth is detectable and can cause a change in the output of the FF. If the position of the noise pulse is just right, noise with some minimum combination of amplitude and frequency will cause a second transition of Vth. The noise does not need to be of a large amplitude if the frequency is high enough. It is not uncommon for power distribution system (PDS) noise to have energy in the GHz range which can cause a rising edge of the signal to be non-monotonic even with low amplitude noise.

.----------- / / Vth(H) --------/--- / / Vth(L) -----/------ / /

---------'

,----------- Output /

---------------'

Monotonic edge - Hysteresis - one transition of Vth(H)

Add hysteresis and there will be different thresholds for the rising edge and for the falling edge. Since only the rising edge creates transitions on the output the Vth(L) is not directly observable.

.----------- / / Vth(H) --------/\/---------- / / Vth(L) -----/--------------- / /

---------'

,----------- Output /

---------------'

Non-monotonic edge - Hysteresis - one detectable transition of Vth(H)

With a hysteretic input, noise added to the signal will cause a second crossing of Vth(H), but if it does not cross Vth(L) in between, the second crossing will not cause an action in the FF.

.----------- / / Vth(H) --------/\------/------ / \ / / \ / Vth(L) -----/------\/--------- / /

---------'

,-----, Output / \

---------------' '------------

Non-monotonic edge - Hysteresis - two detectable transitions of Vth(H)

Only if the rising edge has sufficient noise to cause crossing of both transitions will two output changes be detected when the input has hysteresis. This can be a large improvement in noise immunity.

So not only will hysteresis improve noise immunity, it is easily measured even on a clock input that is only sensitive to one edge of the clock.

Also because then the clock event is all over before the first stage of the flop has a chance to respond, so any super-fast junk on the edge can at most cause a bit of jitter.

Yup. In big systems, clock distribution is not at all trivial, but we're talking about one flipflop here.

I suspect the OP's problem was a ringy clock pulse interacting with two different logic thresholds in the different parts--one saw multiple clocks and the other didn't.

Cheers

Phil Hobbs

Well, try it and see what happens.

Schmitts are handy in SPI slaves, where the wiring to the chip can be sloppy. As long as the data string isn't chained.

I've seen chips whose sd output was delayed a half-cycle, output on clock falling edge, to remove the clock skew hazard.

Sometimes I add an RC delay, or just a resistor, to the sd connection to add prop delay to the data, to reduce clock skew hazards.

This uses one 272-bit shift register to drive the relays. It has multiple clock buffers and long routes, a clear skew hazard. So it has added resistors.

The TPIC6595 relay drivers do have schmitt inputs. It works fine.

Seems like you'd still have the same clock skew problem, Schmitt or no.

Sensible. The master-slave flipflop idea, circa 1960. ;)

Well, in a relay driver you don't need to run the SPI at 50 MHz.

Cheers

Phil Hobbs