74HC74 pulse shaping

A set-reset flip flop can be made with two inverting amplifiers (originally, Eccles and Jordan did it with vacuum tubes). Two transistors is enough. The WAY it is made, is with positive feedback (collector of Q1 to base of Q2, and collector of Q2 to base of Q1). Two-gates SR flip-flops are a bit cleaner than the simple Eccles-Jordan circuits, don't require capacitor pulse coupling. They still use positive feedback, though. In a '555, the accurate hysteresis is achieved by using a logic-type SR flip flop (with its internal positive feedback) and comparators to set thresholds, The comparators don't have any feedback or hysteresis.

The '74 inputs for Set and Reset functions have the wrong polarity to do both functions from a single input signal. If a '555s internal comparators had the wrong-polarity connections, it wouldn't work as a Schmitt either. This has nothing to do with any distinction between analog and digital.

Exactly. The 555 and '74 are totally different parts. Why are you comparing them? The FF within the 555 has nothing to do with the Schmitt trigger capability. That comes from using the two reference values set by the two comparators.

An *analog* comparator can be turned into a Schmitt trigger by adding positive feedback to the input circuit. Or alternatively negative feedback can be added to the reference input if there is one.

A FF uses digital feedback using separate inputs to the gates for the FF inputs and the feedback. It is not possible to use the feedback within the FF to make a Schmitt trigger. If the FF has appropriate inputs, you can use the FF as a gate and *add* feedback, but why not just use a gate in the first place?

No, the buffer will not necessarily draw virtually no current.

It will draw very little current **if** fed logic-level inputs, but as you approach the threshold there must be an increase in supply current as the input transistors are biased into conduction but not quite at threshold for switching. I don't see that specified anywhere for the few single gate ST buffers.

NXP specifies a **typical** peak supply current of more than 0.4mA for a 74HC14 at 4.5V.

--sp

Because both contain a set/reset flip flop.

True.

False. If the /Set and /Reset of the 7474 were amended to be Set and /Reset (i.e. if you had active-true Set function), then you could connect Input -> resistor_divider ->Set Input ->/Reset

and you'd have hysteresis functionally the same as any Schmitt trigger.

You could also use feedback from the Q and /Q to accomplish this, but that's not essential.

But adding positive feedback around a comparator doesn't always work right. It doesn't have positive feedback until the input has worked its way to the output, so you can generally propagate a fast glitch that fools the hysteresis.

Once you get down to single electrons, all circuits are digital :-)

This thread is over a year old, but I came across it while searching for so mething in this same vein. I had breadboarded an HC74 as a divider, when I blew the chip up with a misplaced jumper wire. The chip was socketed so I popped in another. Whoa, no more divide by two, just lots of bogus triggeri ng! What gives? Turns out that the Philips/NXP part that I had been using incorporates a built-in Schmitt stage on the clock input. Others don't. Isn't this a violation of some International Standard? Sure wish they all were like the NXP; had to add an HC14 to be universally compatible.

I believe that the cannonical 7474 has a regular input on the clock; it's up to you to make sure the clock is clean, or to figure out how to convince your supply chain to buy the specific part that works.

And note: if NXP doesn't SAY on the data sheet that there's a Schmitt trigger there, then there's no guarantee that the next one you buy with the identical part number will have one. Semiconductor manufacturers will move parts to new fabs, and the characteristics will change. I used to maintain a board where every year or so we'd have to trim resistor values around an MC1594 as the chip characteristics changed.

I don't think a Schmitt trigger is an aspect of the fab process. I believe that has to be designed in. So changing fabs shouldn't affect it.

True. So far, so good...

I started wondering if the breadboard has a loose wire; often a CMOS chip will function, powered through its inputs, if Vdd ad Vss are not both connected.

Then it occurred to me, how would one know that the clock input had hysteresis? 'HC74 outputs are only sensiitive to the falling edge. One never knows WHAT the threshold is for a rising edge, it has no output-signal consequences.

The International Standard is TI's data sheet. The TI data sheet specifies a minimum clock rise/fall time.

Most logic is unhappy with slow clock edges. Once you start clocking more than one chip, clock skew is deadly and schmitts won't help. So adding a schmitt to a flipflop clock input is silly.

Philips originally developed the HEF4000 series which had superior properties to 74HC and 74HCT. I think some 74-series devices were also available as 74HEFxxx. Maybe they now sell the original HEF series as HC?

HC74's are rising-edge triggered on their clock inputs. Preset and clear are level-sensitive active-low.

Are you plonking Rickman? That makes sense.

Not sure what *PLONK* means in this context. A clock input can have hysteresis and it can be measured. You can't do it with a simple pulse though. Hysteresis would be protecting against noise on the rising edge of the clock making the rising edge no longer monotonic. To measure this you would need to create such a non-monotonic rising edge and then see at what point it generates more than one clock pulse. It doesn't need to be fast, in fact it can be much easier to measure the result if the rising edge is slower.

Hmmm.... should I say *PLONK* back at cha?

Once again John is sailing unknown waters (to him). Clock skew is unavoidable, either inside chips or on boards. So the skew has to be managed to work with you rather than against you.

Nothing else he said has any value in this discussion. A minimum rising edge rate is orthogonal to input hysteresis.

eh ??

'HC74 clocks on POSITIVE-going edge, and there's a specification for MINIMUM input slew rate (rise-time). ...Jim Thompson

Yeah, my sign error. It's not about polarity. To observe hysteresis, one has to observe an output with low-to-high input and with high-to-low input. An edge triggered clock input doesn't give you two observable output events, only one.

You can't test this chip for hysteresis on the clock input.

You could apply a sine wave with a DC offset, from a function generator, and tease the amplitude and offset to see what the trigger band is. But an HC74 isn't spec'd to have hysteresis.

Many SPI chips have explicit schmitts on their clock, or all, inputs, which can be handy. Or, if you cascade the data chain, dangerous.

Simply clocking a multi-chip shift register, or a multi-flop state machine, takes some care.

Of course you can. I've already explained how to do it. You don't even need any fancy equipment other than maybe an arbitrary waveform generator.