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Xilinx Constraints Question

Hello group,

We are modelling our ASIC in an FPGA (Spartan) for system testing and as a demonstrator.

For power reasons, we have globally (centrally) gated clocks of frequency f, f/2, f/4 etc (named clk_div2, clk_div4) Both the clocks and the gating signals (clk_en) are distributed to the endpoints so that in the FPGA we only have one clock of frequency f (named clk)

For the FPGA, I add a BUFG at the root of clock f, use a generic to disable all clock gates, and apply a constraint for the frequency.

The question is : How do I constrain the frequency f/2, f/4 etc. The synthesis tool optimizes nets clk_div2, clk_div4 so that only one net exists (clk), so I have no where to put the constraints (or do select all endpoints).

(I currently add constraints via the UCF).

Any suggestions or pointers grreatly appreciated.

Thanks,

Steven

Reply to
moogyd
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Hi Steven,

If possible, stick with the single clock constraint on the main clock with a frequency of f. This will cause the delay between flip flops in the logic intended to be clocked by clk_div2 and clk_div4 to be 2* and 4* faster than really necessary, but will keep things simple, and easy. Everything should work just the same. Unfortunately, you may find that the clk_div2 and clk_div4 regions are nowhere near meeting timing with this constraint. In that case, you will need to relax timing in those areas using "multi-cycle paths". I suggest that you read up on this subject, and look in the Help for your tools as to how to apply them. I always try to avoid multi-cycle paths, as verification that they are done correctly requires a timing simulation after place and route. (e.g. A functional (non-timing) simulation will not find a problem where your logic samples the value out of the multi-cycle path earlier than it is available). My simulator crashes due to lack of memory under Win 32 whenever I have tried a post place and route timing simulation. I guess that you will have to run such simulations for the ASIC, so this might not be a problem for you.

Good Luck,

Ken Morrow, Morrow Electronics Limited

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Reply to
kenm

Hi Steven, OK, your system sounds like you have one clock, witth clock enables for the slower bits. That's a good thing.

So, you constraints should be something like this.

NET "clock_div_2_enable*" TNM="slow_ffs"; TIMESPEC TS1 = FROM : slow_ffs : TO : slow_ffs : 20ns;

I added a wildcard at the end of the clock enable signal because often the synthesis tool will duplicate nets that go to a lot of desitinations. This will hopefully catch that situation. Also, be careful not to generate the enable signal by feeding it back to itself, or the tool will include the FF used to make the enable in the timegroup. You don't want that as the enable has to get to every destination in the time determined by the clock period, not the relaxed multi-path delay. For example, have a counter and use it to generate the enables.

HTH., Syms.

p.s. Here's a freebie puzzle I remembered while typing this. What's the only word that's an anagram of itself?

Reply to
Symon

Good idea, I hadn't thought of using the enable to define the timing groups - I was looking at the clock only.

Stifle :-) ?

Thanks,

Steven

Reply to
moogyd

My pleasure.

Very good! :-) Cheers, Syms.

Reply to
Symon

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