timing constraint is impossible to meet

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Hi All,

When compiling a design I receive the following message:

:Pack:1653 - At least one timing constraint is impossible to meet because
   component delays alone exceed the constraint.  A physical timing constraint
   summary will appear in the map report.  This summary will show a MINIMUM net
   delay for the paths.  For more information about the Timing Analyzer, consult
   the Xilinx Timing Analyzer Reference manual.  For more information on TRCE,
   consult the Xilinx Development System Reference Guide "TRACE" chapter.

The problem however is that I receive no information WHICH SIGNAL PATH
generates that problem, so I'm not able to redesign my core...
The timing constraints are already the most liberal to be accepted by external
hardware.

How to identify the path generating the problem?
I can not run the timing analyzer, because the map fails.
--
TIA & regards,
Wojtek Zabolotny

Re: timing constraint is impossible to meet
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Hi Wojtek,
In the ISE GUI (I'm using 8.2 at the moment; I hope your version is
similar), find the 'Processes' window. Expand the section 'Implement
Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If you
double-click 'Analyze Post-Map Static Timing', it'll churn away and
eventually open the timing analyser. You can then find what path is failing.
The key insight is to run the timing analyser on the map results, before you
enter the P&R phase.
HTH, Syms.



Re: timing constraint is impossible to meet
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The problem is, that I can not 'Generate Post-Map Static Timing',
because the map fails!
--
Wojtek

Re: timing constraint is impossible to meet

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Relax the timing until it maps, then you can find the slowest paths (at
PAR if necessary). Fix these and retry. Then tighten the timings a bit.
Repeat until done.

It's frustrating, I agree. Map should have completed, just to let you
run the report.

Alternatively, what did synthesis report as the longest paths? Did they
exceed your timing constraints? It may be worth fixing those first.
(However, synthesis may not see the longest path if you are using black
box components)

- Brian


Re: timing constraint is impossible to meet
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  I've seen a similar issue, but it wasn't related to clock period
constraints. The offset in constraint was applied to input pins that had
some combinatorial logic before getting latched by a flop. The offset in
wasn't too tight by itself, but the extra combinatorial cloud was making
it impossible to meet, hence a similar error.
  Start looking at offset in/out constraints, since it sounds like your
clock constraints are relaxed enough.

HTH,
-P@

Re: timing constraint is impossible to meet

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OK, soz that didn't help you, ISE 8.2 doesn't seem to behave like that, I've
only experienced this problem when it does the timing stuff in P&R. Out of
interest, what version of the tools are you using? It sounds like a big
backwards step from what I'm used to! Maybe there's a switch to turn off
timing driven mapping?
Cheers, Syms.
p.s. What Brian posted! :-)



Re: timing constraint is impossible to meet
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Here one point is not clear to me. How a timing constraint forces the
map to fail.If every thing (in the design) is correct then it passes
the map with timing errors.I think there is some problem in the design
which is forcing the map to fail.

Re: timing constraint is impossible to meet

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Try this environmental variable before running P&R

set XIL_TIMING_ALLOW_IMPOSSIBLE=1

Hans
www.ht-lab.com



Re: timing constraint is impossible to meet
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Can I mention the deep and abiding love I have for whoever decided that
the options to MAP needed to be passed through a combination of command
line arguments, settings files, and nearly undocumented environment
variables, with any given setting only accessible through one of those?
  That hasn't complicated my build chain one tiny bit, nosireebob.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Re: timing constraint is impossible to meet

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Seconded!

Martin

--
snipped-for-privacy@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
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Re: timing constraint is impossible to meet

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Hey, that's not fair... When I want to do a "never ifdef" by
testing an env var or macro that is sure to be absent, I usually
use IMPOSSIBLE_THINGS_BEFORE_BREAKFAST - and that one is getting
awfully, awfully close :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: timing constraint is impossible to meet
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I think the OP's problem is that he has set the timing driven packing
and placement option for Map.  Turning this off allows map to complete
and generate the timing so you can find the failing path.  In essence,
turning on timing driven packing and placement allows map to do the
first half of place & route.  This is where the timing error prevents
map
completion.

Regards,
Gabor

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