Hi
I have an evaluation board with a target and a control FPGA. The control FPGA is connected to the target FPGA over 32-bit local bus and can write the data to a host PC over a RS232 interface. Both FPGAs are internally clocked with 24MHz. So I have to implement on the control FPGA a transmitter that gathers the 32 bits and sends them in 8 bit chunks to the host PC. I wonder if somebody has some helpful ressources how to implement such an simple interface. Also I have to implement a suitable divisor for the baudgenerator to generate 115200 Hz from 24MHz.
Would be thankful for helpful comments and ressources ;)
Dan!