I have simulated the delays on Xilinx OSERDES using both the ISE simulator and ModelSimXE and find that the delay in serial output does not match the specifications in the user guide. Has anyone had a similar experience? There is suppose to be at least a one framing clock delay and a variety of serial clocks delay depending on the data width.
Moving the design to hardware I find a seemingly random delay by comparing the output of an OSERDES to a framing clock (CLKDIV) outputted by an ODDR.
Only by outputting the CLKDIV signal by another OSERDES did I find any synchonization between CLKDIV and the data:
cam_oserdes_xclk: cam_link_out_sdr_oserdes port map( clk => cam_clk_280, -- in clkdiv => clkdiv, -- in data => "1100011", -- in 7 bits q => xclk ); -- out
This works great. Did anyone else have an issue using ODDR?
Brad Smallridge aivision