Multichannel Opb Memory Controller question

whatever you connect to OPB bus can not have access to memory on XCL as cachelink FSL bus is accessible only from MicroBlaze, not from busses connected to MB

As usual, my english is terrible... I'm sorry! I try to be more clear.

Microblaze will access sdram through XCL. Microblaze will NOT be connected to opb bus.

An external micro will access sdram through OPB bus. It will be a master, the only master of the opb bus. The memory controller will be the only slave of opb bus.

Is it reliable?

Can Microblaze write a region of sdram and "simultaneously" external micro read another region?

Sorry again!

Marco

"Marco T." schrieb im Newsbeitrag news:drcqlq$um5$ snipped-for-privacy@nnrp.ngi.it...

almost anything can be made reliable, but what you are suggesting is not REASONABLE.

if SDRAM is on XCL then whatever external micro should access the SDRAM controller that does arbitration directly - using OPB here is not a good idea.

Antti

So, a better approach, could be that external micro accesses sdram through another XCL channel?

I dont have found lots of information about developing a XCL master peripheral.

What is your suggestion?

Thanks Antti, your help is always precious!

Marco

"Marco T." schrieb im Newsbeitrag news:drcrch$v1f$ snipped-for-privacy@nnrp.ngi.it...

you need sdram controller that has XCL port to microblaze and defined by interface to your external micro.

Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze uses 2 port. Now I should develop a XCL Master interface and connect it to one of the 2 free ports.

But I don't have found any document about it. Only about connecting microblaze to memory. I could insert two microblaze into the project, but in what way may I execute different softwares?

The second microblaze should only read and trasmit datas out of fpga.

Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze

Marco, I need to the the same thing. Let's keep in touch one each other! Besides... if your english is a problem... are you Italian ? I am.

I'll have a MB connected to OPB, using 2 XCL ports for cache; MCH_SDRAM_OPB, some UARTs, all on OPB. Then I need to develop two XCL "masters" to read/write high speed data from the remaining two XCL channels.

Can we help one each other ?

Hello Antonio, I have opened also a webcase about this trouble. They told me to watch mch_opb_ipif core, into cores directory.

But it seems to be still not ready for use.

Marco

Unfortunately there is no document solely about the XCL bus.

But read the small section in MicroBlaze reference guide on the XCL signals and also look at the timing diagrams in the mch_opb_sdram controller.

If it's still unclear email me and I will try to answer your questions.

Göran Bilski