Memory Controller

If I have two or more sections of logic in my FPGA that need to read and write to the same memory, what is the typical/standard approach to control who writes/reads when? Is there an example somewhere that I could look at? Thanks, JTW

It's a problem more general than just memory, ie. you could be sharing other devices. For the most general case you need some kind of interconnect structure and arbitration, like for example Avalon (offered by Altera) or WISHBONE (notably used by OpenCores, though I couldn't seem find a bus arbiter).

Often however, you can use system specific knowledge to adopt a simpler solution, such as running the memory at twice the speed, using odd cycles for one device, and even for the other (rarely works for external memory though).

Tommy