Hi, I'm trying to learn the way to work with output buffers and other features of the XC3S1000FG456 installed on my Analog Devices FPGA extender board. This board has 3 connectors placed in such a way to be able to connect it to a Blackfin DSP evaluation board, but it can work stand-alone as a normal Spartan3 evaluation board and that's the way I'm using it now. I wanted to push out a signal and see how it behaves changing slew, drive current and IO standard (the 3 attributes of the OBUF template). I made a couple of examples in VHDL and I'd like you to tell me what you think about the 2 different approaches.
First one:
OBUF_inst_slow : OBUF generic map ( DRIVE => 16, IOSTANDARD => "LVCMOS33", SLEW => "SLOW") port map ( O => slow_out, -- slow_out is the out port of my entity (same for fast) I => slow_sig_out -- slow_sig_out is the signal I want to send out (same for fast) );
OBUF_inst_fast : OBUF generic map ( DRIVE => 16, IOSTANDARD => "LVCMOS33", SLEW => "FAST") port map ( O => fast_out, -- Buffer output (connect directly to top-level port) I => fast_sig_out -- Buffer input );
I places this snippet inside the architecture of my code and "check syntax" tells me there are no errors in the VHDL.
Second one, I commented the previous code and inserted the following lines in the declaration part of the architecture section:
attribute slew : string; attribute SLEW of fast_out : signal is "FAST"; attribute SLEW of slow_out : signal is "SLOW";
then I put these assignments just before the end of the behavioural section:
fast_out