Memory gate count in ASIC and in FPGA

First of all I would suggest to forget the "gate count" numbers from the FPGA vendors and look at the features of the FPGA. To build a ROM in an FPGA is easiest using dedicated block memory of the device. Most FPGA's allow memory to be generated from distributed logic cell elements. In the case of a ROM, you can generate the memory you need from LUTs in the FPGA fabric even if the distributed memory is not available, but it will be a bigger headache.

block memory. Note that the datasheet counts bits not bytes so you're talking 2.4 Megabits - something like a Virtex-II 6000 "6 million gate" - but of course that leaves pretty much all of the logic resources for the rest of your design.

Hi Xing1

Your 300Kbyte ASIC rom would use up about 150 BRams assuming 16Kbit useage (18b might take some less.

If thats is mostly Firmware then thats alot of Bram to use up for 1 item. I generally budget 1Bram at about $1 of FPGA cost so thats alot of $ cost and also note that Asic rom is maybe 10x-20x cheaper than regular sram in same process so using Brams for just code storage might be extravagent. You could look at storing that off chip and use that BRam as cache if its for a cpu or work out an external Flash interface.

If by chance you were storing very high precision coeff tables that you could also synthesize with an engine or two, that may well take up far less resources, something you could care less perhaps in an ASIC but FPGAs are just not that cheap Yet!

Is it Firmware or coeff data?

regards

johnjakson at usa dot com

Thanks Gabor and JJ for your reply.

If I really want to implement the 300KMbyte ROM in FPGA, I guess I have to use at least Xilinx Virtex II 6000, which has 144 Block RAM(totally

The question comes from an eveluation of an hardware IP, which has 500K logic gate counts in ASIC plus 300KByte ROM. When I consider if I can implement it in FPGA, the first thing is what FPGA and how many FPGAs I need for. For this case, I can barely get ROM done on Virtex 6000, but not sure if the rest resource of 6000 can accomendate the 500K logics. Do I have to synthesis the Logic in Synplicity and place&route it to know how many slices it requires? or there is a way so that I can know in advance?

Thanks.

have

RAM(totally

A memory-centric part like the SX35 would likely be a lot more cost effective (or to be fair, maybe an Altera EP2S60). Something that hasn't been discussed is how your ROM is organized though. If it is 8 bits wide and hugely deep, it may be challenging to meet timing with the address lines needing to go to all corners of the chip (or muxing the outputs, although perhaps you can use tri-state bus). Or if it is organized as a bunch of strange sized ROM's, you may end up with parts of some ROM's being wasted in the FPGA (meaning that you need more than

but

logics.

know

Not only do you need to know the size of the design when it is targetted to an FPGA (using Synplify or some other synthesis tool), but you need to know how fast it will run. In my experience, ASIC designers almost ignore their levels of logic. If your ASIC is that way, it may not meet the speed targets you need when targetted to an FPGA.

Good luck,

Marc

Then what's the best way to know how fast my logic can run on the FPGAs? Do I have to use the synthesis(from synplify for example) result to fgiure out the maximum frequency? any other methods?

THanks!

Marc Randolph wrote:

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Howdy,

Synthesis tools can give you a first order approximation of the maximum frequency, but unless you have some experience with the design and know what place and route will do with it, I'd be skeptical until I'd run it all the way through at least once. There are just too many variables (high fanout and many levels of logic being the two largest) involved with an unknown design, especially if it is coming from an ASIC.

Good luck,

Marc