Hi, We are currently using virtexIIpro and virtex4 fpga to prototype a dsp processor. All the code is synthesizable verilog and we are using Xilinx ISE to do synthesis and place and route. Everything works fine and the processor runs at full speed (50Mhz). However, this is only good for functionnal verification on the bench. The ASIC flow and the FPGA flow are very different so the actual gates in the FPGA are different than what will be on the ASIC. For example, we can't use the FPGA to verify the test vectors and scan chains that the test engineer is working on.
Is it possible to prototype the EXACT same gates that will be in the ASIC? We use Synopsys Design Compiler to generate the ASIC gates. Basically is there a way to take the gates generated by Design Compiler, and map them in the FPGA? We don't really care if this runs slower, but it would allow the test engineer to start working on all the test vectors before we receive silicon.
Thank you very much, David