Followup to:
> By author: "Jerry"
> In newsgroup: comp.arch.fpga
> > >
> > > I come from the ASIC side, and I have
> > > > something in verilog like: assign Z = (a[15:0] / b[9:0]); and I get
an
> > > error saying the divisor must be a power of 2. Looking around, it
> > > > seems that this cannot be implemented into HW??
> > >
> > > The limitation is with your synthesis tool, not the capabilities of
FPGA.
> >
> > > > Any advice is appreciated.
> > >
> > > Buy a good book on computer arithmetic and implement the
> > > operation yourself
> > > (or alternatively search a bit hardware around the web and you're
bound to
> > find some example code). Don't expect the resultant hardware to be
small.
> To expand on what JonB said, there is a trade off between gate count and
> > number of clock cycles required to perform the operation.
> To further expand...
> Something that reads in Verilog like what you have above is
> all-combinatorial logic, meaning no loops and no latches. Not even
> microprocessors usually have combinatorial dividers, because of the
> sheer amount of area required; you may want to see if you can't use a
> clocked design instead. Common designs are 1, 2 or 4 bits per clock.
Algorithms like that used in the IBM 360/91 or Cray-1 could be implemented as combinatorial dividers. An iterative algorithm like the 360/91, or fully pipelined like the Cray-1 could also be implemented depending on the required speed and available clock.
Possibly implemented in combination with the block RAM a reasonably efficient implementation might be possible.
-- glen