asic gate count

Hi, I am looking for some tool / ip that can give me approximate gate count of mapper/demapper. Any helpful hint is greatly welcome.

Thanks, Vijayant

Reply to
vijayant.rutgers
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To get a gate count ... you have to synthesize it, the synthesis will give you an area and typical a "gate" is a 2 input NAND gate. So divide you're total area by the area of the NAND gate and that is your gate count.

Mike

Reply to
Mike Lewis

The traditional method for ASIC is to divide the number of transistors by the number of transistors in a 2 input NAND gate. For CMOS, that is four.

Good or bad, that is the usual way.

-- glen

Reply to
glen herrmannsfeldt

What is your method for determining how many transistors are in the design? My synthesis tools only give me area.

Mike

Reply to
Mike Lewis

Divide the area of your design by the area of a 2-input NAND with lowest drive strength * 4.

Cheers, Jon

Reply to
Jon Beniston

Mike Lewis wrote: (snip)

(snip)

Last I knew, they gave transistors, but that was some time ago.

For FPGA it is much harder to give a reliable count, and you are asking in an FPGA newsgroup.

If it gives gate counts different types of gates and with a little guessing on transistors/gate. Is this for standard cell, sea of gates, or something else? I thought I used to have pretty detailed information on the standard cell libraries, including transistors for each library element.

-- glen

Reply to
glen herrmannsfeldt

I have a design on FPGA that is ready. However, we need to have some mapping from fpga design to asic. I know that this will not be accurate. But accuracy is not our concern right now. We just need upper bound. Also, we are also looking for some IP Core for ASIC so that we can rough estimate.

Regards, Vijayant

gn?

Reply to
vijayant.rutgers

Take the nuber of registers and combinatorial cells used for the fpga. Start with the registers, inspect if you have register doubling in synthesis for load balance and ask yourself if you need this register doubling. In ASIC you have often load balancing with buffering. For combinatorical logic you should have a look, what type of cells is in your vendors library. For a lot of technologies the tool will more likely use 3 input cells instead of 4 input cells. This will roughly increase your combinatorical cell count by 10%-30% (it depends on the design). You should take into account, that you need to add something like 10% buffering for global nets and timing correction that comes for free in an fpga.

bye Thomas

Reply to
Thomas Stanka

One approach is to run it through the Xilinx tools and review the map report (.mrp file). If you take this approach, I suggest eliminating memory blocks (PPC if used) and DSP/multiplier blocks and re-running, to understand how much of the gate count comes from these blocks.

- Brian

Reply to
Brian Drummond

Hi Vijayant, every "rule of thumb" you are trying to use will give you a misleading result. Even if you just want a maximum value.

The only way to get a nearly accurate number is to synthesize your design with an asic synthesis tool using the desired technology library.

You may use a default synthesis at first, to get an idea of the size and gate count. These results may vary depending on your design goals. If you want to increase speed your design may become larger. If speed is negotiable the design may become smaller with some area optimization constraints.

However, the result of this synthesis will be an area value (most likely in square micro meters) because the used gates (and flipflops) heavily vary in size and transistor count. Unless you are using a sea of gates technology that has only nand2-elements.

To give you an idea think about this:

If you have a simple 4to1 mux, this may be synthesized with a single mux4 cell in some standard cell technologies. With a sea of gates technology you need a bunch of nand2's for this function, plus some routing resources. So, how would you express the number of gates in these two cases? The mux4 is just the solution with the minimum number of cells. depending on your constraints the result might be any correct combination of simpler gates.

Also, the gate count, however calculated is not relevant for production. Only the area tells you how many chips can be fabricated on a single waver. And the area changes with the used technology of course. So 1000 gates in a 130nm technology yield less chips per waver than 2000 gates in a 45nm technology. (rough estimation, just to give you an idea)

So forget gate counts if you want to compare technologies. Only use of gate counts is if you want to compare designs using the same technology. And I mean the very same technology! (Just take a look at some of the fruitless gate count discussions about Brand-A and Brand-X FPGAs)

Have a nice synthesis Eilert

snipped-for-privacy@gmail.com schrieb:

Reply to
backhus

Just wanted to argue on your last point .. gate count is the easiest means to compare technologies. It will stay relatively constant from tech to tech and you will have the nand2 area for the technology you are in so you can roughly compare the area of a design for different technologies using the gate count for the design.

Mike

Reply to
Mike Lewis

On Fri, 30 May 2008 13:53:44 -0400, "Mike Lewis" >

Only if you ignore the possibility of the use of high drive strength gates. If your design is at the boundary of just meeting timing in a process the actual gates used in your design will most probably require higher drive strengths and your actual gate count will be higher than what you'd have guessed by just looking at logic requirements. Then when you port to the next lower feature process, your relative gate count change will be much higher than what you expect. As an example a NAND2X4 might be %50 larger than a NAND2X1 and the former might be needed in one process where as the latter would do in another.

Reply to
Muzaffer Kal

Mike Lewis schrieb:

Hi Mike, Muzaffer added a good point about drive strength, and another one is that the area of different gate-cells (e.g. xor2) differ heavily from a nand2. Even worse when looking at FFs-cells. And, the libraries give you no multiplication factor based on the nand2 area, so you have to calculate all these for yourself for up to hundreds of different cells. (easy???) One more thing is that the use of more complex cells saves routing area. how will you put that in your calculation? And these are just points that show how misleading a gatecount-value would be for comparing standard cell technologies. Comparing different technologies like FPGA and standard cells would make even less sense.

The area calculated by the synthesis (or layout) tool gives you a value you can work with. And for FPGAs this would be the number of LUTs and FFs (plus some vendor specific stuff if necessary).

And even these values for themselves can only be seen as one aspect of a specific implementation. Because area can change heavily when you are optimizing the very same design with different constraints. The area may vary by a factor of two or three. (is 200% variation good, even for a rough compare?)

In the end it's just another number. And like many others only useful if you know more about the background of it.

And of course it depends on what you want to do with that number. (e.g. Megapixels for digital cameras...nice to see them increase, but what good is further increase when the pictures become worse due to noise? The marketing guys love it anyway because the average custumer don't know.)

Best regards Eilert

PS.: Just some funny story... I'm preparing a lab course for FPGA synthesis and compared the technology schematic views of XILINX ISE and Mentor Precision RTL. ISE shows the equivalent logic inside a LUT as a bunch of 2 input gates and inverters while Precision RTL uses big N input gates with bubbles.

It's all inside a LUT and uses the same resources, but confronted with pictures of the same LUT drawn in these two styles needs some time to tell that they show the same.

Reply to
backhus

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