ISE Webpack 8.1 adder wierdness

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The first two examples produce 16 4-input LUTs on a Spartan 3 and the
third produces only 8 4-input LUTs.  Is there a way to get ISE to use
only 8 LUTs without adding flipflops or resorting to a structural
(XORCY, MUXCY, etc.) description?

module adder_test_16_luts_1(a, b, c, result);
    input[7:0] a, b;
    input c;
    output[8:0] result;

    assign result = a + (~b) + c;
endmodule

module adder_test_16_luts_2(a, b, c, result);
    input[7:0] a, b;
    input c;
    output[8:0] result;

    wire[8:0] inv_b = ~b;
    assign result = a + inv_b + c;
endmodule

module adder_test_8_luts(clk, a, b, c, result);
    input clk;
    input[7:0] a, b;
    input c;
    output[8:0] result;

    reg[8:0] inv_b;
    always @(posedge clk) inv_b <= ~b;
    
    assign result = a + inv_b + c;
endmodule


Todd


Re: ISE Webpack 8.1 adder wierdness
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Have you tried with

assign result = (~b) + a + c;

?


    Sylvain

Re: ISE Webpack 8.1 adder wierdness
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Oooh, good idea.  Trying it now...  Whoa! this one used 22!  For
reference, here is the 22-LUT version:

module adder_test_22_luts(a, b, c, result);
    input[7:0] a, b;
    input c;
    output[8:0] result;

    assign result = (~b) + a + c;
endmodule

Todd


Re: ISE Webpack 8.1 adder wierdness

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I strongly guess that the flipflop has normal and inverted output.
Therefore you get the inversion for free (for the cost of these flipflops).
And furthermore it seems to be, that the pure combinational solutions
are slightly to complex to fit into 8 LUTs (the inversion is too much to
fit).

Ralf

Re: ISE Webpack 8.1 adder wierdness
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I don't see any reference to an inverted output on the flipflops in the
Spartan 3 data sheet.  From looking at the slice diagram in the DS and
the schematic for ADSU8 in the library guide, it looks like the LUTs
should be able to absorb the inverter on b.

Todd


Re: ISE Webpack 8.1 adder wierdness
Todd Fleming schrieb:

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any signal inversion at LUT inputs are of couse "absorbed" so it
should no make any difference if signals are inverted or not.

Antti


Re: ISE Webpack 8.1 adder wierdness
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Well not always. In this case, yes it should because only 'b' is
inverted. But if 'a' and 'b' were to be inverted, that couldn't be
pushed into the LUTs because one of the two input has to feed the
carry chain. The only modification that could be done on 'a' is AND
it (with the MULAND (not sure of the name)).

The slice stucture allow pretty tricky/complex stuff to be done in just
1 layer, but I found it's often quite difficult to make xst understand ...


     Sylvain

Re: ISE Webpack 8.1 adder wierdness
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I kept trying various approaches but was unable to find a way to get
XST to synthesize an efficient structure, so I resorted to a structural
description with XORXY and MUXCY using Verilog's generate.

Todd


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