Xilinx ISE 8.1 Makefile

I guess in previus versions that wouldn't have been too hard with a little Perl-script. But in ISE8.1 they changed to a proprietary binary format for the project-file, so it's kind of hard to make sense out of it. Unless someone has by now found a way to decode it properly, that is.

cu, Sean

Here is sample .bat file that I typically use for command line synthesis ... that bypasses gui entirely. There are lots of advantages to command line flow ... Entire synthesis flow is documented ( and can be archived) in text document. Portability of synthesis flow among workstations/PCs is ensured - not determined by check box in a nested dialog box.

Take a look at the developers reference guide in the Xilinx install path /Xilinx/doc/usenglish/books/docs/dev/dev.pdf. This document describes all command line options for various utilities.

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cd .. rmdir /s /q synth mkdir synth cd synth

xst -ifn ..\scripts\xst.txt -intstyle xflow

ngdbuild %1.edf -p xc3s400-4-pq208 -uc ..\files\%1.ucf

map -k 6 -detail -pr b %1 rem pause

par -ol med -w %1.ncd %1_r%2

copy %1.pcf %1_r%2.pcf

trce -e -o %1_err.twr %1_r%2 trce -v -o %1_ver.twr %1_r%2

rem ************************************************** rem * first make bitgen for rom, then remake for JTAG rem ************************************************** rem bitgen -w -g UserID:55550%2 %1_r%2 %1_r%2 bitgen -w -g UserID:55550%2 -g DonePipe:yes -g UnusedPin:Pullup %1_r%2 %1_r%2

Sanka Piyaratna schrieb:

Hi Sanka, not from the projectfile anymore, as said in a previous posting, but from other files:

the command.log file the *.prj file(s), containing a list of the used sources the *.xst file(s), containing the XST option settings

You can learn more about these files by reading the XFLOW documentation. The XFLOW tool targets skript based use of the ISE tools, like the one John posted.

Skripts are a good thing, but make-ing has still some advantages. If you succeed in any way with your idea, let us know!

have a nice synthesis Eilert

is there a way to handle some incremental flow with makefiles ..?

I know the process from c-programming ... only modified files need to compile - but all of them need to be linked ...

could that save some time for FPGAs as well? the synthezize step only needs to handle modified files ... as I understand the flow the next step is merging everything (and optimizing across modules)?

bye, Michael

Here is a link to a makefile app note on the XESS website:

FYI: Taking a look inside an .ise file, I think it is a sequence of FIP files concatenated.

If you break the ISE file into lots of smaller files (dividing them by the "PK" flags), you will get lots of zip files whose contents may be peeked with a zip file extractor

Best regards,

Zara

I know synplify and xst support incremental synthesis flow, but they do it with user constraints not makefiles.

HTH, Jim