FPGA imp

I respond as this newsgroup responds to all questions of this type (we need an FAQ):

This highly depends on

- throughput

- FIR-length

- word width

- other constraints (linear phase filter?, many 0 coefficients?)

Try to ask again.

Kolja Sulimma

hai,

FIR Filter specifications are 256-tap,16-bit input and coefficients width,linear phase filter..

which type will give high computational speed with minimum area??

1.Linear convolution 2.Circular buffering which is most advisable architecture?? 1.canonical form 2.Transpose form

regards, faz

througput and area are contradicting optimization goals, therefore you can't minimize both at the same time. Usually you have a throughput goal and then minimize the area under that throughput constraint.

Circular buffering is not a meaningful in a hardware implementation.

For those parameters you can roughly expect for a virtex 5:

Parallel: 400 Msps with 128 multipliers. Serial: 1,5Msps with a single multiplier. There are intermediate forms and you can push parallelization further to compute more than one sample per clock.

Note however: While the filter can run at those clock rates it might be difficult to build a complete system at these speeds, let alone do data IO.

Kolja Sulimma

ed

hai,

I got one more doubt in FIR filter implementation...Though the basic operation is MAC...It is different from normal convolution operation performed manually(with pencil and paper)...

for ex x(n)=3D{1,2,3} h(n)=3D{2,1,4} Then y(n)=3DN1+N2-1=3D3+3-1=3D5 y(n)=3D{2,5,12,11,12}

But in canonical form of FIR implementation with the same formula:

y(n)=3D{2,5,12} because shift of x(n) till number of taps(i.e.number of filter coefficients which is 3 here)

why this difference??kindly explain..

regards, faz

Because you stopped the second computation too soon, so you only got the first three samples out. Try it with the sequence x(n)=... 0, 0, 0, 1, 2, 3, 0, 0, 0,...

- Brian