Hai,
1.Can i set the clock frequency of the FIR filter at any frequency i want... but pretty much higher than the sample rate? for example :Fc=3.5khz Fs=8khz can i clock as any value >8khz say 1Mhz(considering the max clock for target device)2.Whether direct form non-symmetric filter structure can support symmetric coefficients??whether the response computed in non-symmetric structure is same as symmetric filter structure?? I knew resource utlization wise symmetric need more adder at the cost of multpliers..
3.In addition to impulse test(basic test to check FIR filter operation before implementing to FPGA),step test,sine wave test.What are other test that has to be compulsorily performed in time domain to check the proper working filter operation before giving any arbitary input to the filter??regards, faz